Searched hist:2009 (Results 751 - 775 of 951) sorted by relevance

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/gem5/src/cpu/checker/
H A Dthread_context.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
diff 6029:007c36616f47 Wed Apr 15 16:13:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Get rid of the Unallocated thread context state.
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
- InOrderCPU's setThreadRescheduleCondition.
- ThreadContext::exit(). This function was there to avoid terminating
simulation when one thread out of a multi-thread workload exits, but we
need to find a better (non-cpu-centric) way.
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
/gem5/src/cpu/o3/
H A Dregfile.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
diff 6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
diff 6221:58a3c04e6344 Tue May 26 12:23:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: add a type for thread IDs and try to use it everywhere
H A Drob.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6221:58a3c04e6344 Tue May 26 12:23:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: add a type for thread IDs and try to use it everywhere
/gem5/src/arch/arm/
H A Dutility.ccdiff 6759:98101a5f7ee4 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Begin implementing CP15
diff 6757:d86d3d6e5326 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Boilerplate full-system code.
diff 6735:6437ad24a8a0 Tue Nov 10 23:34:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Implement fault classes.

Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
diff 6246:5744fafb5072 Sun Jun 21 12:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Clear out some inherited hangers on in util.isa and utility.hh.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/
H A DSConstructdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6655:380a32b43336 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access
diff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6168:ba6fe02228db Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false
diff 6157:eaf2fd8f54c0 Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.
diff 6143:010490fd482a Mon May 04 19:58:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: re-work the *Source functions to take more information.
Start by turning all of the *Source functions into classes
so we can do more calculations and more easily collect the data we need.
Add parameters to the new classes for indicating what sorts of flags the
objects should be compiled with so we can allow certain files to be compiled
without Werror for example.
diff 6121:18aff7f548c1 Tue Apr 21 20:17:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: Rename the basic environment from env -> main.
env is used as a local variable all over the place and sometimes it is
easy to get confused as to whether the global env or local env is being
used. This will become especially important when I change the way we
support our variants.
diff 6120:4dcea6c903fa Tue Apr 21 20:17:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: Fix two problems with the way that the library path is generated.
1) -L is automatically added, so don't do it ourselves
2) prepend the paths for gzstream and libelf so they are certain to
come first. The problem is that python might add /usr/lib to the path
and the user might have a locally installed version of libelf installed.
diff 6113:4e008e4ecc92 Tue Apr 21 13:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: make default target work again
diff 6108:66014cd0dc61 Tue Apr 21 11:17:00 EDT 2009 Nathan Binkert <nate@binkert.org> SCons: Export export_vars so SConsopts files can add to them
/gem5/src/cpu/simple/
H A Dtiming.ccdiff 6739:48d10ba361c9 Wed Nov 11 00:10:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Mem: Eliminate the NO_FAULT request flag.
diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 6221:58a3c04e6344 Tue May 26 12:23:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: add a type for thread IDs and try to use it everywhere
diff 6102:7fbf97dc6540 Mon Apr 20 00:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Mem: Change isLlsc to isLLSC.
diff 6076:e141cc7896ce Sun Apr 19 07:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Memory: Rename LOCKED for load locked store conditional to LLSC.
diff 6043:19852407f5c9 Sun Apr 19 05:23:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: If the simple CPU is already idle, just return from suspendContext, don't assert.
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 6012:47748a3b6ecf Thu Mar 12 02:05:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> cpu: fix minor endian issue with trace output
(no functional change)
/gem5/configs/common/
H A DOptions.pydiff 6776:463aab78c057 Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> m5: Added option to take a checkpoint at the end of simulation
diff 6769:630a3d0b7eb7 Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> m5: Moved profile option since Simulation depends on it.
diff 6641:59f08019c39a Wed Sep 16 09:45:00 EDT 2009 Korey Sewell <ksewell@umich.edu> configs: add maxinsts option on command line
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.
diff 6174:7e5c7412ac89 Tue May 05 02:39:00 EDT 2009 Korey Sewell <ksewell@umich.edu> cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
diff 6144:e330f7bc22ef Tue May 05 02:51:00 EDT 2009 Korey Sewell <ksewell@umich.edu> cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
diff 5869:acbe11bbfe68 Tue Feb 10 18:49:00 EST 2009 Korey Sewell <ksewell@umich.edu> Configs: Add support for the InOrder CPU model
/gem5/src/arch/alpha/isa/
H A Ddecoder.isadiff 6804:e8e64ad04260 Sun Dec 20 16:03:00 EST 2009 Soumyaroop Roy <sroy@cse.usf.edu> Alpha: Implement MVI and remaining BWX instructions.
diff 6739:48d10ba361c9 Wed Nov 11 00:10:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Mem: Eliminate the NO_FAULT request flag.
diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 6076:e141cc7896ce Sun Apr 19 07:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Memory: Rename LOCKED for load locked store conditional to LLSC.
diff 5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations.
diff 5808:baf5d5c96c68 Sat Jan 24 10:27:00 EST 2009 Nathan Binkert <nate@binkert.org> pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.
It's instantaneous and so it's somewhat bogus, but it's a first step.
/gem5/src/arch/sparc/
H A Disa_traits.hhdiff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6326:008930a4ace5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined RegFile class.
diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 6110:5051aafec8d5 Tue Apr 21 11:17:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
H A Dprocess.hhdiff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
diff 5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
/gem5/src/cpu/
H A Dthread_state.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
diff 6324:a535b2232c08 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Move the PCs out of the ISAs and into the CPUs.
diff 6221:58a3c04e6344 Tue May 26 12:23:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: add a type for thread IDs and try to use it everywhere
diff 6031:be16ad28822f Wed Apr 15 16:18:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ThreadState: initialize status to Halted in constructor.
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
diff 5999:3cf8e71257e0 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: Fix all stats usages to deal with template fixes
H A DBaseCPU.pydiff 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
diff 6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
diff 6116:a5a97b04d796 Tue Apr 21 18:40:00 EDT 2009 Nathan Binkert <nate@binkert.org> arm: Unify the ARM tlb. We forgot about this when we did the rest.
This code compiles, but there are no tests still
diff 6023:47b4fcb10c11 Thu Apr 09 01:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> tlb: More fixing of unified TLB
diff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
diff 5821:2831ae658bfc Fri Jan 30 19:08:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Config: Cause a fatal() when a parameter without a default value isn't set(FS #315).
H A Dstatic_inst.ccdiff 6192:6cd5f0282d8a Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder-tlb-cunit: merge the TLB as implicit to any memory access
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
diff 5870:5645632d594c Wed Feb 11 01:19:00 EST 2009 Nathan Binkert <nate@binkert.org> style
/gem5/src/sim/
H A Dpseudo_inst.ccdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 6118:a1d388751779 Tue Apr 21 18:40:00 EDT 2009 Nathan Binkert <nate@binkert.org> pseudo: only include kernel stats if FULL_SYSTEM.
diff 5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations.
diff 5882:5a047c3f3795 Mon Feb 23 14:48:00 EST 2009 Nathan Binkert <nate@binkert.org> debug: Move debug_break into src/base
diff 5808:baf5d5c96c68 Sat Jan 24 10:27:00 EST 2009 Nathan Binkert <nate@binkert.org> pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.
It's instantaneous and so it's somewhat bogus, but it's a first step.
H A Dpseudo_inst.hhdiff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5808:baf5d5c96c68 Sat Jan 24 10:27:00 EST 2009 Nathan Binkert <nate@binkert.org> pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.
It's instantaneous and so it's somewhat bogus, but it's a first step.
/gem5/src/arch/alpha/
H A Dtypes.hhdiff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
H A Dinterrupts.hhdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 5810:606de5b3d116 Sun Jan 25 23:29:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Add a setCPU function to the interrupt objects.
/gem5/src/base/loader/
H A Dsymtab.hhdiff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations.
/gem5/src/arch/mips/isa/formats/
H A Dfp.isadiff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
/gem5/src/arch/x86/isa/microops/
H A Dfpop.isadiff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 5788:6d4161a36ca1 Wed Jan 07 01:55:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Autogenerate macroop generateDisassemble function.
/gem5/src/mem/cache/prefetch/
H A Dstride.ccdiff 6010:a1e71f3576f8 Tue Mar 10 20:37:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> prefetch: don't panic on requests w/o contextID (e.g., writebacks).
diff 5875:d82be3235ab4 Mon Feb 16 11:56:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
/gem5/tests/configs/
H A Dsimple-timing-ruby.pydiff 6289:a9e7d19871b5 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Fix RubyMemory to work with the newer ruby.
6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests.
H A Dsimple-timing-mp-ruby.pydiff 6289:a9e7d19871b5 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Fix RubyMemory to work with the newer ruby.
6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests.
/gem5/src/base/
H A Dbitfield.hhdiff 6274:117dbbf0e1e2 Thu Jul 02 01:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a findLsbSet function and use it to implement clz.
diff 6215:9aed64c9f10f Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: use base/types.hh not inttypes.h or stdint.h
/gem5/src/mem/slicc/
H A Dparser.pydiff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc

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