History log of /gem5/src/base/bitfield.hh
Revision Date Author Comments
# 14046:9eecb7504759 28-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix ctz32 for systems where unsigned int is not 32bit

The implementation of ctz32 uses __builtin_ctz to count the number of
trailing zeros and therefore makes the assumption that an unsigned int
is 32bit. This change checks whether that's the case and if not it
uses __builtin_ctzl instead.

Change-Id: Ic3ed3ada25fd0a93c7eb91d75b954e9924bdbb77
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19129
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>


# 14045:219770957562 26-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Add function to count trailing zeros in a 64-bit integer

Change-Id: Iaad0679b403bc5015ffeacbf7284313e41a36cd0
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19128
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>


# 13824:54e92033cf67 14-Mar-2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu>

dev-arm: Correct cast of template parameter

Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.

This patch add a compile-time static cast that remove the error
when clang is used.

Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


# 13531:e6f1bf55d038 11-Oct-2018 Jairo Balart <jairo.balart@metempsy.com>

dev-arm: Add a GICv3 model

Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>


# 12226:36dff288b076 17-Oct-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Function for mirroring bits in variable length word

This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.

Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


# 11932:98961d1b51ca 24-Mar-2017 Sascha Bischoff <sascha.bischoff@arm.com>

dev: Align BAR0 size to power of 2 for VirtIO devices

When setting the size of a PCI BAR, the kernel only supports powers of
two (as per the PCI spec). Previously, the size was incorrectly read
by the kernel, and the address ranges assigned to the PCI devices
could overlap, resulting in gem5 crashes. We now round up to the next
power of two.

Kudos to Sergei Trofimov who helped to debug this issue!

Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2580
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>


# 11800:54436a1784dc 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.


# 10537:47fe87b0cf97 14-Nov-2014 Andreas Hansson <andreas.hansson@arm.com>

arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.


# 10400:0655a3d869ad 24-Apr-2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

misc: Add functions for doing popcount and power-of-two checking

Adds two public domain algorithms for determining number of set bits and also
whether a value is a power of two, uses the builtin that is available in GCC
and clang for popcount.


# 6274:117dbbf0e1e2 02-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

ARM: Add a findLsbSet function and use it to implement clz.


# 6215:9aed64c9f10f 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: use base/types.hh not inttypes.h or stdint.h


# 4680:09867d787df8 14-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Move bitunion code into it's own file.


# 4661:44458219add1 22-Jun-2007 Korey Sewell <ksewell@umich.edu>

mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".


# 4649:899f745b3c21 08-May-2007 Gabe Black <gblack@eecs.umich.edu>

Fix insertBits so it doesn't shift things into oblivion


# 4425:e94d396daad9 09-May-2007 Ali Saidi <saidi@eecs.umich.edu>

bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer.

src/base/bitfield.hh:
bit_val was being used directly in the statement in
return. If type B had fewer bits than last, bit_val << last would get
the wrong answer.


# 4275:8a37341c7507 21-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Missed a const


# 4274:638f735c9bc7 20-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Fixed up some types and const placement, and added signed bitfields that sign extend themselves.


# 4262:e851cdcf279b 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Ditched read or write only subbitfields for now since they were proving difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match.


# 4261:0a667162b5fa 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

For the _BitfieldRO and _BitfieldWO classes, make sure the undesired operator is redefined as private.


# 4260:cb8a68017b41 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Formatting fixes.


# 4259:ca1ca13665ba 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Lots and lots of comments.


# 4258:a84b8cce90ce 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Reworked the BitUnion stuff a bit. There is moderately better isolation of the backend parts, although there are still macros.


# 4257:337f01885f36 17-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Created BitUnion type which lets you define nested bitfields for an integer in a portable way.


# 4244:18391d0467c6 15-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

fix a bug gabe found


# 4103:785279436bdd 03-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore


# 4070:74449a198a44 18-Feb-2007 Ali Saidi <saidi@eecs.umich.edu>

implement vtophys and 32bit gdb support

src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic


# 3814:33bd4ec9d66a 04-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

More changes to get SPARC fs closer. Now at 1.2M cycles before difference

configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller


# 3422:426a8ebd677c 26-Oct-2006 Gabe Black <gblack@eecs.umich.edu>

Added a few functions to stuff values into bitfields in an instruction.


# 3386:6094e8865bb8 23-Oct-2006 Gabe Black <gblack@eecs.umich.edu>

Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh>


# 2665:a124942bacb8 31-May-2006 Ali Saidi <saidi@eecs.umich.edu>

Updated Authors from bk prs info


# 2632:1bb2f91485ea 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.