Searched hist:2008 (Results 201 - 225 of 494) sorted by relevance
/gem5/src/dev/alpha/ | ||
H A D | backdoor.hh | 5480:b9460d7f74f0 Tue Jun 17 23:36:00 EDT 2008 Nathan Binkert <nate@binkert.org> rename AlphaConsole to AlphaBackdoor |
/gem5/src/dev/x86/ | ||
H A D | speaker.hh | 5636:27a9526eea1f Sat Oct 11 05:16:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices. |
H A D | speaker.cc | 5636:27a9526eea1f Sat Oct 11 05:16:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices. |
/gem5/src/sim/ | ||
H A D | debug.hh | diff 5512:755fcaf7a4cf Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> RemoteGDB: add an m5 command line option for setting or disabling remote gdb. |
H A D | pseudo_inst.hh | diff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode. diff 5741:323dac95e72c Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> pseudo inst: Add rpns (read processor nanoseconds) instruction. This instruction basically returns the number of nanoseconds that the CPU has been running. diff 5505:90d6811d5ea6 Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> m5ops: clean up the m5ops stuff. - insert warnings for deprecated m5ops - reserve opcodes for Ali's stuff - remove code for stuff that has been deprecated forever - simplify m5op_alpha diff 5504:288b54c2fd8d Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: fix indentation and formatting of the pseudo insts. |
/gem5/src/arch/mips/linux/ | ||
H A D | linux.cc | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | system.cc | diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. |
/gem5/src/base/ | ||
H A D | inifile.cc | diff 5544:65b27e939646 Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> inifile: Whack preprocessor access. We haven't used the preprocessor feature of the inifile stuff in a very long time, so let's get rid of it since it would otherwise take effort to maintain. |
H A D | intmath.hh | diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases. |
H A D | socket.cc | diff 5523:6279e78a2df2 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. |
H A D | cprintf.cc | diff 5756:88038cdbb9e1 Wed Dec 03 07:57:00 EST 2008 Nathan Binkert <nate@binkert.org> cprintf: support a configurable width and precision ("*" in printf) |
/gem5/src/cpu/ | ||
H A D | nativetrace.cc | diff 5523:6279e78a2df2 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. |
/gem5/src/arch/alpha/linux/ | ||
H A D | process.hh | diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. |
/gem5/src/kern/solaris/ | ||
H A D | solaris.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/arch/x86/isa/formats/ | ||
H A D | formats.isa | diff 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode. |
H A D | cpuid.isa | 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode. |
/gem5/src/arch/alpha/ | ||
H A D | kernel_stats.hh | diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage. |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | seqop.isa | diff 5692:0d6addcde185 Mon Oct 13 02:29:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Set the delayed commit flag in x86 microops appropriately. diff 5663:be5cb9485aed Sun Oct 12 18:53:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an eret microop which returns from ROM to combinational decoding. diff 5662:4f3371a1c58c Sun Oct 12 18:43:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make Br never report itself as the last microop. 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them. |
/gem5/src/arch/mips/ | ||
H A D | pagetable.hh | diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases. |
/gem5/src/arch/x86/isa/insts/general_purpose/ | ||
H A D | semaphores.py | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/arch/riscv/isa/formats/ | ||
H A D | fp.isa | 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/cpu/o3/ | ||
H A D | O3Checker.py | diff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes. |
/gem5/src/cpu/simple/ | ||
H A D | BaseSimpleCPU.py | 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
/gem5/src/dev/sparc/ | ||
H A D | T1000.py | diff 5478:ca055528a3b3 Tue Jun 17 23:29:00 EDT 2008 Nathan Binkert <nate@binkert.org> Rename SimConsole to Terminal since it makes more sense |
/gem5/src/mem/cache/prefetch/ | ||
H A D | stride.cc | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
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