12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292SN/A */ 302SN/A 315882Snate@binkert.org#ifndef __SIM_DEBUG_HH__ 325882Snate@binkert.org#define __SIM_DEBUG_HH__ 332SN/A 346214Snate@binkert.org#include "base/types.hh" 355512SMichael.Adler@intel.com 368278SAli.Saidi@ARM.com/** @file This file provides the definitions for some useful debugging 378278SAli.Saidi@ARM.com * functions. These are intended to be called from a debugger such as 388278SAli.Saidi@ARM.com * gdb. 398278SAli.Saidi@ARM.com */ 408278SAli.Saidi@ARM.com 418278SAli.Saidi@ARM.com 428278SAli.Saidi@ARM.com/** Cause the simulator to execute a breakpoint 439960Sandreas.hansson@arm.com * @param when the tick to break 448278SAli.Saidi@ARM.com */ 459960Sandreas.hansson@arm.comvoid schedBreak(Tick when); 462SN/A 4711157SDylan.Johnson@ARM.com/** 4811164SDylan.Johnson@ARM.com * Cause the simulator to execute a breakpoint 4911164SDylan.Johnson@ARM.com * relative to the current tick. 5011164SDylan.Johnson@ARM.com * @param delta the number of ticks to execute until breaking 5111164SDylan.Johnson@ARM.com */ 5211164SDylan.Johnson@ARM.comvoid schedRelBreak(Tick delta); 5311164SDylan.Johnson@ARM.com 5411164SDylan.Johnson@ARM.com/** 5511157SDylan.Johnson@ARM.com * Cause the simulator to execute a breakpoint when 5611157SDylan.Johnson@ARM.com * the given kernel function is reached 5711157SDylan.Johnson@ARM.com * @param funcName the name of the kernel function at which to break 5811157SDylan.Johnson@ARM.com */ 5911157SDylan.Johnson@ARM.comvoid breakAtKernelFunction(const char* funcName); 6011157SDylan.Johnson@ARM.com 618278SAli.Saidi@ARM.com/** Cause the simulator to return to python to create a checkpoint 628278SAli.Saidi@ARM.com * @param when the cycle to break 638278SAli.Saidi@ARM.com */ 648278SAli.Saidi@ARM.comvoid takeCheckpoint(Tick when); 658278SAli.Saidi@ARM.com 668278SAli.Saidi@ARM.com/** Dump all the events currently on the event queue 678278SAli.Saidi@ARM.com */ 688278SAli.Saidi@ARM.comvoid eventqDump(); 698278SAli.Saidi@ARM.com 705512SMichael.Adler@intel.comint getRemoteGDBPort(); 715512SMichael.Adler@intel.com// Remote gdb base port. 0 disables remote gdb. 725512SMichael.Adler@intel.comvoid setRemoteGDBPort(int port); 735512SMichael.Adler@intel.com 745882Snate@binkert.org#endif // __SIM_DEBUG_HH__ 75