Searched hist:13999 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | misc.cc | diff 13999:a26c2e234a80 Tue Feb 19 05:20:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Change mcrMrc15TrapToHyp signature This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | misc.isa | diff 13999:a26c2e234a80 Tue Feb 19 05:20:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Change mcrMrc15TrapToHyp signature This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | utility.cc | diff 13999:a26c2e234a80 Tue Feb 19 05:20:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Change mcrMrc15TrapToHyp signature This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | utility.hh | diff 13999:a26c2e234a80 Tue Feb 19 05:20:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Change mcrMrc15TrapToHyp signature This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | miscregs.cc | diff 13395:0f064dae9f6b Wed Oct 31 12:45:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch32 RVBAR RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.hh | diff 13395:0f064dae9f6b Wed Oct 31 12:45:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch32 RVBAR RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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