Searched defs:reg (Results 26 - 50 of 56) sorted by relevance

123

/gem5/src/cpu/o3/
H A D	dyn_inst.hh	187 const RegId& reg = si->destRegIdx(idx); variable
H A D	free_list.hh	76 void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); } argument
/gem5/src/cpu/
H A D	simple_thread.hh	640 readVecLaneFlat(RegIndex reg, int lId) const argument 647 setVecLaneFlat(RegIndex reg, int lId, const LD &val) argument [all...]
/gem5/src/arch/x86/
H A D	cpuid.cc	80 uint64_t reg = 0; local
H A D	interrupts.cc	197 ApicRegIndex reg = decodeAddr(offset); local 214 ApicRegIndex reg = decodeAddr(offset); local 372 X86ISA::Interrupts::readReg(ApicRegIndex reg) argument 410 setReg(ApicRegIndex reg, uint32_t val) argument [all...]
H A D	interrupts.hh	240 setRegNoEffect(ApicRegIndex reg, uint32_t val) argument
H A D	types.hh	89 Bitfield<5,3> reg; member in namespace:X86ISA
/gem5/src/cpu/minor/
H A D	dyn_inst.cc	140 printRegName(std::ostream &os, const RegId& reg) argument [all...]
/gem5/src/arch/alpha/
H A D	ev5.hh	70 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } argument 71 inline Addr DTB_PTE_PPN(uint64_t reg) argument 73 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } argument 74 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } argument 75 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> argument 76 DTB_PTE_FONW(uint64_t reg) argument 77 DTB_PTE_GH(uint64_t reg) argument 78 DTB_PTE_ASMA(uint64_t reg) argument 80 ITB_ASN_ASN(uint64_t reg) argument 81 ITB_PTE_PPN(uint64_t reg) argument 83 ITB_PTE_XRE(uint64_t reg) argument 84 ITB_PTE_FONR(uint64_t reg) argument 85 ITB_PTE_FONW(uint64_t reg) argument 86 ITB_PTE_GH(uint64_t reg) argument 87 ITB_PTE_ASMA(uint64_t reg) argument 89 MCSR_SP(uint64_t reg) argument 91 ICSR_SDE(uint64_t reg) argument 92 ICSR_SPE(uint64_t reg) argument 93 ICSR_FPE(uint64_t reg) argument 95 ALT_MODE_AM(uint64_t reg) argument 96 DTB_CM_CM(uint64_t reg) argument 97 ICM_CM(uint64_t reg) argument [all...]
H A D	stacktrace.cc	278 StackTrace::decodeSave(MachInst inst, int &reg, int &disp) argument 316 int reg, disp; local
/gem5/src/arch/arm/kvm/
H A D	gic.cc	115 uint64_t reg; local 130 uint64_t reg = value; local
/gem5/src/dev/arm/
H A D	gpu_nomali.cc	207 NoMaliGpu::readReg(nomali_addr_t reg) argument 223 NoMaliGpu::writeReg(nomali_addr_t reg, uint32_t value) argument 247 NoMaliGpu::writeRegRaw(nomali_addr_t reg, uint32_t value) argument [all...]
H A D	generic_timer.cc	315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) argument 421 GenericTimer::readMiscReg(int reg, unsigned cpu) argument 511 GenericTimerISA::setMiscReg(int reg, RegVal val) argument 518 readMiscReg(int reg) argument [all...]
/gem5/src/arch/arm/tracers/
H A D	tarmac_record.cc	151 TraceRegEntry( const TarmacContext& tarmCtx, const RegId& reg) argument
/gem5/src/arch/mips/
H A D	mt.hh	56 readRegOtherThread(ThreadContext *tc, const RegId &reg, argument 80 setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val, argument 104 readRegOtherThread(ExecContext *xc, const RegId &reg, ThreadID tid=InvalidThreadID) argument 111 setRegOtherThread(ExecContext *xc, const RegId& reg, RegVal val, ThreadID tid=InvalidThreadID) argument [all...]
H A D	stacktrace.cc	169 StackTrace::decodeSave(MachInst inst, int &reg, int &disp) argument 207 int reg, disp; local
H A D	dsp.cc	1128 MipsISA::simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt) argument 1140 MipsISA::simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign) argument
/gem5/src/sim/
H A D	fd_entry.hh	83 HBFDEntry(HBFDEntry const& reg, bool close_on_exec = false) argument 121 FileFDEntry(FileFDEntry const& reg, bool close_on_exec = false) argument 233 SocketFDEntry(SocketFDEntry const& reg, bool close_on_exec = false) argument [all...]
/gem5/src/systemc/core/
H A D	scheduler.cc	149 Scheduler::reg(Process *p) function in class:sc_gem5::Scheduler
/gem5/src/arch/arm/
H A D	miscregs.cc	989 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) argument 1025 canWriteCoprocReg(MiscRegIndex reg, SC argument 1061 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) argument 1068 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) argument 1079 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc) argument 1098 int reg = -1; local 1112 unflattenMiscReg(int reg) argument 1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument 1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument [all...]
/gem5/src/cpu/simple/
H A D	exec_context.hh	181 const RegId& reg = si->srcRegIdx(idx); variable 191 const RegId& reg = si->destRegIdx(idx); variable 202 const RegId& reg = si->srcRegIdx(idx); variable 213 const RegId& reg variable 223 const RegId& reg = si->srcRegIdx(idx); variable 233 const RegId& reg = si->destRegIdx(idx); variable 244 const RegId& reg = si->destRegIdx(idx); variable 257 const RegId& reg = si->srcRegIdx(idx); local 292 const RegId& reg = si->destRegIdx(idx); local 323 const RegId& reg = si->srcRegIdx(idx); variable 334 const RegId& reg = si->destRegIdx(idx); variable 343 const RegId& reg = si->srcRegIdx(idx); variable 352 const RegId& reg = si->destRegIdx(idx); variable 362 const RegId& reg = si->destRegIdx(idx); variable 371 const RegId& reg = si->srcRegIdx(idx); variable 380 const RegId& reg = si->destRegIdx(idx); variable 389 const RegId& reg = si->srcRegIdx(idx); variable 398 const RegId& reg = si->destRegIdx(idx); variable [all...]
/gem5/src/arch/hsail/
H A D	operand.hh	603 RegOperandType reg; member in class:RegAddrOperand [all...]
/gem5/src/dev/net/
H A D	ns_gige.cc	216 uint32_t &reg = *pkt->getPtr<uint32_t>(); local 427 uint32_t reg = pkt->getLE<uint32_t>(); local [all...]
H A D	sinic.cc	246 uint32_t reg = regData32(raddr); local 252 uint64_t reg = regData64(raddr); local 1307 std::string reg = csprintf("vnic%d", i); local 1486 std::string reg = csprintf("vnic%d", i); local [all...]
/gem5/src/cpu/checker/
H A D	cpu.hh	194 const RegId& reg = si->srcRegIdx(idx); variable 202 const RegId& reg = si->srcRegIdx(idx); variable 213 const RegId& reg = si->srcRegIdx(idx); variable 224 const RegId& reg variable 235 const RegId& reg = si->destRegIdx(idx); variable 244 const RegId& reg = si->destRegIdx(idx); variable 253 const RegId& reg = si->destRegIdx(idx); variable 262 const RegId& reg = si->destRegIdx(idx); variable 272 const RegId& reg = si->destRegIdx(idx); local 305 const RegId& reg = si->srcRegIdx(idx); variable 312 const RegId& reg = si->srcRegIdx(idx); variable 320 const RegId& reg = si->destRegIdx(idx); variable 328 const RegId& reg = si->srcRegIdx(idx); variable 368 const RegId& reg = si->destRegIdx(idx); variable 377 const RegId& reg = si->destRegIdx(idx); variable 386 const RegId& reg = si->destRegIdx(idx); variable 396 const RegId& reg = si->destRegIdx(idx); variable 406 const RegId& reg = si->destRegIdx(idx); variable 415 const RegId& reg = si->destRegIdx(idx); variable 487 const RegId& reg = si->srcRegIdx(idx); variable 495 const RegId& reg = si->destRegIdx(idx); variable [all...]

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Indexes created Thu Sep 26 06:36:22 EDT 2019