arch/alpha/ev5.hh

70 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
71 inline Addr DTB_PTE_PPN(uint64_t reg)
72 { return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
73 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
74 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
75 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
76 inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
77 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
78 inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
80 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
81 inline Addr ITB_PTE_PPN(uint64_t reg)
82 { return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
83 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
84 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
85 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
86 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
87 inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
89 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
91 inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
92 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
93 inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
95 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
96 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
97 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }