| /gem5/src/arch/power/insts/ |
| H A D | floating.cc | 36 FloatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:FloatOp
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| H A D | misc.cc | 36 MiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MiscOp
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| H A D | mem.cc | 38 MemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MemOp
44 MemDispOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:MemDispOp
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| H A D | condition.cc | 36 CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:CondLogicOp
49 CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:CondMoveOp
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| H A D | static_inst.cc | 59 PowerStaticInst::generateDisassembly(Addr pc, function in class:PowerStaticInst
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| H A D | integer.cc | 37 IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:IntOp
84 IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:IntImmOp
120 IntShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:IntShiftOp
147 IntRotateOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:IntRotateOp
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| H A D | branch.cc | 63 BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:BranchPCRel
87 BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:BranchNonPCRel
109 BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:BranchPCRelCond
135 BranchNonPCRelCond::generateDisassembly(Addr pc, function in class:BranchNonPCRelCond
161 BranchRegCond::generateDisassembly(Addr pc, function in class:BranchRegCond
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| /gem5/src/arch/hsail/insts/ |
| H A D | gpu_static_inst.cc | 49 HsailGPUStaticInst::generateDisassembly() function in class:HsailISA::HsailGPUStaticInst
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| /gem5/src/arch/x86/insts/ |
| H A D | microfpop.cc | 56 std::string FpOp::generateDisassembly(Addr pc, function in class:X86ISA::FpOp
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| H A D | micromediaop.cc | 39 std::string MediaOpReg::generateDisassembly(Addr pc, function in class:X86ISA::MediaOpReg
53 std::string MediaOpImm::generateDisassembly(Addr pc, function in class:X86ISA::MediaOpImm
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| H A D | microldstop.cc | 47 std::string LdStOp::generateDisassembly(Addr pc, function in class:X86ISA::LdStOp
63 std::string LdStSplitOp::generateDisassembly(Addr pc, function in class:X86ISA::LdStSplitOp
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| /gem5/src/arch/arm/insts/ |
| H A D | data64.cc | 46 DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataXImmOp
55 DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataXImmOnlyOp
65 DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataXSRegOp
74 DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataXERegOp
83 DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataX1RegOp
94 DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataX1RegImmOp
106 DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataX1Reg2ImmOp
118 DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataX2RegOp
131 DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataX2RegImmOp
145 DataX3RegOp::generateDisassembly(Add function in class:ArmISA::DataX3RegOp
160 DataXCondCompImmOp::generateDisassembly( function in class:ArmISA::DataXCondCompImmOp
173 DataXCondCompRegOp::generateDisassembly( function in class:ArmISA::DataXCondCompRegOp
188 DataXCondSelOp::generateDisassembly( function in class:ArmISA::DataXCondSelOp
[all...] |
| H A D | branch.cc | 47 BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchReg
56 BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchImm
65 BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::BranchRegReg
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| H A D | sve_mem.cc | 46 SveMemVecFillSpill::generateDisassembly(Addr pc, function in class:ArmISA::SveMemVecFillSpill
62 SveMemPredFillSpill::generateDisassembly(Addr pc, function in class:ArmISA::SveMemPredFillSpill
78 SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::SveContigMemSS
97 SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::SveContigMemSI
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| H A D | pred_inst.cc | 48 PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::PredIntOp
65 PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::PredImmOp
79 DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataImmOp
88 DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataRegOp
97 DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::DataRegRegOp
106 PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:ArmISA::PredMacroOp
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| H A D | branch64.cc | 73 BranchImmCond64::generateDisassembly( function in class:ArmISA::BranchImmCond64
83 BranchImm64::generateDisassembly( function in class:ArmISA::BranchImm64
93 BranchReg64::generateDisassembly( function in class:ArmISA::BranchReg64
103 BranchRet64::generateDisassembly( function in class:ArmISA::BranchRet64
114 BranchEret64::generateDisassembly( function in class:ArmISA::BranchEret64
123 BranchImmReg64::generateDisassembly( function in class:ArmISA::BranchImmReg64
135 BranchImmImmReg64::generateDisassembly( function in class:ArmISA::BranchImmImmReg64
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| /gem5/src/arch/sparc/insts/ |
| H A D | micro.cc | 37 SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::SparcMacroInst
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| H A D | priv.cc | 40 Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::Priv
50 RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::RdPriv
63 WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::WrPriv
83 WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::WrPrivImm
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| H A D | trap.cc | 38 Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::Trap
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| H A D | blockmem.cc | 38 BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::BlockMemMicro
63 BlockMemImmMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::BlockMemImmMicro
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| H A D | integer.cc | 83 IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::IntOp
98 IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::IntOpImm
116 SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:SparcISA::SetHi
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| /gem5/src/arch/riscv/insts/ |
| H A D | mem.cc | 48 Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::Load
57 Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::Store
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| H A D | compressed.cc | 44 CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::CompRegOp
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| H A D | standard.cc | 47 RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::RegOp
57 CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const function in class:RiscvISA::CSROp
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| H A D | amo.cc | 47 string MemFenceMicro::generateDisassembly(Addr pc, function in class:RiscvISA::MemFenceMicro
62 string LoadReserved::generateDisassembly(Addr pc, function in class:RiscvISA::LoadReserved
71 string LoadReservedMicro::generateDisassembly(Addr pc, function in class:RiscvISA::LoadReservedMicro
81 string StoreCond::generateDisassembly(Addr pc, function in class:RiscvISA::StoreCond
91 string StoreCondMicro::generateDisassembly(Addr pc, function in class:RiscvISA::StoreCondMicro
102 string AtomicMemOp::generateDisassembly(Addr pc, function in class:RiscvISA::AtomicMemOp
112 string AtomicMemOpMicro::generateDisassembly(Addr pc, function in class:RiscvISA::AtomicMemOpMicro
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