/gem5/src/cpu/testers/directedtest/ |
H A D | RubyDirectedTester.cc | 58 // create the ports 60 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i), 70 for (int i = 0; i < ports.size(); i++) 71 delete ports[i]; 77 assert(ports.size() > 0); 88 if (idx >= static_cast<int>(ports.size())) { 92 return *ports[idx]; 111 assert(idx >= 0 && idx < ports.size()); 113 return ports[idx];
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H A D | RubyDirectedTester.hh | 101 std::vector<MasterPort*> ports; member in class:RubyDirectedTester
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/sc_vector/ |
H A D | sc_vector.cpp | 90 sc_vector<sc_port<i_f> > ports; member in struct:Initiator 93 : ports("ports", 4) 100 for (unsigned int i = 0; i < ports.size(); i++) // Use method size() with vector 103 ports[i]->method(); // Use operator[] with vector 149 port_type ports; // Vector-of-ports member in struct:M 191 : ports("ports", N) 206 sc_assert( ports [all...] |
/gem5/src/systemc/core/ |
H A D | module.cc | 109 panic_if(proxies.size() > ports.size(), 110 "Trying to bind %d interfaces/ports to %d ports.\n", 111 proxies.size(), ports.size()); 114 auto portIt = ports.begin();
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H A D | sc_port.cc | 77 m->ports.push_back(this);
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H A D | module.hh | 127 std::vector<::sc_core::sc_port_base *> ports; member in class:sc_gem5::Module
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/gem5/tests/configs/ |
H A D | memtest-ruby.py | 61 options.ports=32 102 # Tie the cpu port to the ruby cpu ports and
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H A D | rubytest-ruby.py | 62 options.ports=32 104 # Tie the ruby tester ports to the ruby cpu read and write ports
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/gem5/configs/ruby/ |
H A D | MESI_Two_Level.py | 86 # number of cpu ports connected to the tester object, which 104 transitions_per_cycle = options.ports, 148 transitions_per_cycle = options.ports, 199 transitions_per_cycle = options.ports,
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H A D | MOESI_CMP_directory.py | 100 # number of cpu ports connected to the tester object, which 114 transitions_per_cycle=options.ports, 168 transitions_per_cycle = options.ports, 227 transitions_per_cycle = options.ports,
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H A D | MOESI_CMP_token.py | 95 # number of cpu ports connected to the tester object, which 118 transitions_per_cycle=options.ports, 163 transitions_per_cycle = options.ports, 232 transitions_per_cycle = options.ports,
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H A D | MI_example.py | 79 # number of cpu ports connected to the tester object, which 93 transitions_per_cycle=options.ports, 159 transitions_per_cycle = options.ports,
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H A D | MOESI_hammer.py | 94 # number of cpu ports connected to the tester object, which 110 transitions_per_cycle=options.ports, 224 transitions_per_cycle = options.ports,
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H A D | MESI_Three_Level.py | 101 # number of cpu ports connected to the tester object, which 176 transitions_per_cycle = options.ports, 227 transitions_per_cycle = options.ports,
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H A D | Ruby.py | 70 parser.add_option("--ports", action="store", type="int", default=4, 72 for the number of ports.")
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/gem5/src/sim/ |
H A D | cxx_config.hh | 91 /** Similar to ParamDesc to describe ports */ 113 std::map<std::string, PortDesc *> ports; member in class:CxxConfigDirectoryEntry 205 /** Get the peer (connected) ports of the named ports */
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H A D | cxx_manager.cc | 343 /* Find the number of ports that will need binding and set the 345 for (auto i = entry.ports.begin(); i != entry.ports.end(); ++i) { 531 DPRINTF(CxxConfig, "Binding ports of object: %s (%s)\n", 534 for (auto i = entry.ports.begin(); i != entry.ports.end(); ++i) { 543 /* Only handle master ports as binding only needs to happen once 544 * for each observed pair of ports */
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/gem5/src/gpu-compute/ |
H A D | tlb_coalescer.cc | 57 // create the slave ports based on the number of connected ports 63 // create the master ports based on the number of connected ports 204 SlavePort *return_port = sender_state->ports.back(); 205 sender_state->ports.pop_back(); 243 sender_state->ports.push_back(this);
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H A D | gpu_tlb.hh | 306 // TLB ports on the cpu Side 308 // TLB ports on the memory side 348 std::vector<SlavePort*>ports; member in struct:X86ISA::GpuTLB::TranslationState
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H A D | compute_unit.cc | 1101 assert(!translation_state->ports.size()); 1329 assert(!translation_state->ports.size());
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/gem5/src/mem/ |
H A D | snoop_filter.hh | 65 * sharers/ports. The snoop filter ties into the flows of requests 91 // Change for systems with more than 256 ports tracked by this object 104 * Init a new snoop filter and tell it about all the slave ports 107 * @param slave_ports Slave ports that the bus is attached to. 121 // make sure we can deal with this many ports 123 "Snoop filter only supports %d snooping ports, got %d\n", 129 * return a list of other slave ports that need forwarding of the 137 * @return Pair of a vector of snoop target ports and lookup latency. 206 * limits the number of snooping ports supported per crossbar. 249 * Converts a bitmask of ports int [all...] |
/gem5/src/python/m5/ |
H A D | SimObject.py | 195 code('ports["%s"] = new PortDesc("%s", %s, %s);' % 524 # new (or overriding existing) parameters or ports, setting 694 ports = cls._ports.local 738 for port in ports.values() 791 ports = cls._ports.local 895 for port in ports.values(): 928 for port in ports.values(): 1218 # since we will be creating new references for all ports. 1502 # Unproxy ports in sorted order so that 'append' operations on 1503 # vector ports ar [all...] |
/gem5/src/mem/slicc/symbols/ |
H A D | StateMachine.py | 1136 for buf_name, ports in in_msg_bufs.items(): 1137 if len(ports) > 1: 1138 # only produce checks when a buffer is shared by multiple ports 1140 if (${{buf_name}}->isReady(clockEdge()) && rejected[${{port_to_buf_map[ports[0]]}}] == ${{len(ports)}}) 1144 "All ports rejected a message. "
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