/gem5/ext/mcpat/cacti/ |
H A D | area.h | 48 Area():w(0), h(0), area(0) { } 55 return area; 64 void set_area(double a_) { area = a_; } 67 double area; member in class:Area
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H A D | bank.cc | 80 htree_in_add = new Htree2(g_ip->wt, (double) mat.area.w, 81 (double)mat.area.h, 85 htree_in_data = new Htree2(g_ip->wt, (double) mat.area.w, 86 (double)mat.area.h, 90 htree_out_data = new Htree2(g_ip->wt, (double) mat.area.w, 91 (double)mat.area.h, 99 area.w = htree_in_data->area.w; 100 area.h = htree_in_data->area [all...] |
H A D | crossbar.cc | 97 //area of a tristate logic 100 g_area *= 2; // to model area of output transistors 112 area.w = wire_len; 113 area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ; 114 Wire w2(g_ip->wt, area.h); 116 double aspect_ratio_cb = (area.h / area.w) * (n_out / n_inp); 155 double res = g_tp.wire_outside_mat.R_per_um * (area.w + area.h) + 157 double cap = g_tp.wire_outside_mat.C_per_um * (area [all...] |
H A D | router.cc | 199 buffer.area = buff.area; 213 crossbar.area = c_b.area; 233 Arbiter vcarb(vc_count, flit_size, buffer.area.w); 234 Arbiter cbarb(I, flit_size, crossbar.area.w); 269 area.h = I * buffer.area.h; 270 area.w = buffer.area [all...] |
H A D | wire.cc | 153 repeater_spacing = global.area.w; 154 repeater_size = global.area.h; 155 area.set_area((wire_length / repeater_spacing) * 164 repeater_spacing = global_5.area.w; 165 repeater_size = global_5.area.h; 166 area.set_area((wire_length / repeater_spacing) * 175 repeater_spacing = global_10.area.w; 176 repeater_size = global_10.area.h; 177 area.set_area((wire_length / repeater_spacing) * 186 repeater_spacing = global_20.area [all...] |
H A D | component.h | 38 #include "area.h" 51 Area area; member in class:Component
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H A D | uca.cc | 42 int num_banks_ver_dir = 1 << ((bank.area.h > bank.area.w) ? _log2(nbanks) 71 htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 75 htree_in_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 79 htree_out_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 87 htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area [all...] |
H A D | subarray.cc | 56 area.h = cell.h * num_rows; 58 area.w = cell.w * num_cols + 73 area.h = cam_cell.h * (num_rows + 1);//height of subarray is decided by CAM array. blank space in sram array are filled with dummy cells 74 area.w = cam_cell.w * num_cols_fa_cam + cell.w * num_cols_fa_ram 84 assert(area.h > 0); 85 assert(area.w > 0); 100 // //: cam_cell.get_area()*(num_rows+1)*num_cols_fa_cam + sram_cell.get_area()*(num_rows+1)*num_cols_fa_ram);//for FA, this area does not include the dummy cells in SRAM arrays. 105 //for FA, this area includes the dummy cells in SRAM arrays.
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H A D | cacti_interface.cc | 41 #include "area.h" 118 area = cache_ht * cache_len; 125 //area_adjust = sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2)); 131 area = cache_ht * cache_len;
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H A D | nuca.cc | 260 /* find delay, area, and power for wires */ 367 nuca_list.back()->bank_pda.area.h = ures.cache_ht; 368 nuca_list.back()->bank_pda.area.w = ures.cache_len; 444 fr->nuca_pda.area.h, 445 fr->nuca_pda.area.w); 474 fr->h_wire->delay*1e9 / fr->bank_pda.area.w); 551 a * ((*niter)->nuca_pda.area.get_area() / 589 if (((n->nuca_pda.area.get_area() - minval->min_area) / minval->min_area) * 599 nuca->nuca_pda.area.h = 603 nuca->bank_pda.area [all...] |
/gem5/ext/mcpat/regression/ |
H A D | verify_output.py | 87 self.area = None 99 print " Area = %s" % self.area 115 temp_node.area = 0 124 temp_node.area += child.area 133 if not withinTolerance(self.area, temp_node.area): 134 print "WRONG: %s.area = %s != %s" % \ 135 (self.name, self.area, temp_node.area) [all...] |
/gem5/ext/dsent/model/std_cells/ |
H A D | BUF.cc | 97 // Set the cell area 179 // Cache area result 180 double area = 0.0; local 181 area += gate_pitch * getTotalHeight() * 1; 182 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV0_GatePitches").toDouble(); 183 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 184 cache->set(cell_name + "->ActiveArea", area); 185 Log::printLine(cell_name + "->ActiveArea=" + (String)area);
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H A D | INV.cc | 105 // Set the cell area 187 // Cache area result 188 double area = gate_pitch * getTotalHeight() * (1 + getGenProperties()->get("INV_GatePitches").toDouble()); local 189 cache->set(cell_name + "->Area->Active", area); 190 cache->set(cell_name + "->Area->Metal1Wire", area); 191 Log::printLine(cell_name + "->Area->Active=" + (String) area); 192 Log::printLine(cell_name + "->Area->Metal1Wire=" + (String) area);
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H A D | LATQ.cc | 115 // Set the cell area 264 // Cache area result 265 double area = 0.0; local 266 area += gate_pitch * getTotalHeight() * 1; 267 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 268 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV2_GatePitches").toDouble(); 269 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV3_GatePitches").toDouble(); 270 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV4_GatePitches").toDouble(); 271 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ1_GatePitches").toDouble(); 272 area [all...] |
H A D | DFFQ.cc | 121 // Set the cell area 320 // Cache area result 321 double area = 0.0; local 322 area += gate_pitch * getTotalHeight() * 1; 323 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 324 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV2_GatePitches").toDouble(); 325 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV3_GatePitches").toDouble(); 326 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV4_GatePitches").toDouble(); 327 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV5_GatePitches").toDouble(); 328 area [all...] |
H A D | XOR2.cc | 113 // Set the cell area 247 // Cache area result 248 double area = 0.0; local 249 area += gate_pitch * getTotalHeight() * 1; 250 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 251 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV2_GatePitches").toDouble(); 252 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ1_GatePitches").toDouble(); 253 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ2_GatePitches").toDouble(); 254 cache->set(cell_name + "->ActiveArea", area); 255 Log::printLine(cell_name + "->ActiveArea=" + (String) area); [all...] |
H A D | AND2.cc | 112 // Set the cell area 226 // Cache area result 227 double area = 0.0; local 228 area += gate_pitch * getTotalHeight() * 1; 229 area += gate_pitch * getTotalHeight() * getGenProperties()->get("NAND2_GatePitches").toDouble(); 230 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV_GatePitches").toDouble(); 231 cache->set(cell_name + "->ActiveArea", area); 232 Log::printLine(cell_name + "->ActiveArea=" + (String) area);
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H A D | OR2.cc | 107 // Set the cell area 223 // Cache area result 224 double area = 0.0; local 225 area += gate_pitch * getTotalHeight() * 1; 226 area += gate_pitch * getTotalHeight() * getGenProperties()->get("NOR2_GatePitches").toDouble(); 227 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV_GatePitches").toDouble(); 228 cache->set(cell_name + "->ActiveArea", area); 229 Log::printLine(cell_name + "->ActiveArea=" + (String)area);
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H A D | MUX2.cc | 122 // Set the cell area 267 // Cache area result 268 double area = 0.0; local 269 area += gate_pitch * getTotalHeight() * 1; 270 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 271 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV2_GatePitches").toDouble(); 272 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ1_GatePitches").toDouble(); 273 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ2_GatePitches").toDouble(); 274 cache->set(cell_name + "->ActiveArea", area); 275 Log::printLine(cell_name + "->ActiveArea=" + (String) area); [all...] |
H A D | ADDF.cc | 146 // Set the cell area 382 // Cache area result 383 double area = 0.0; local 384 area += gate_pitch * getTotalHeight() * 1; 385 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV1_GatePitches").toDouble(); 386 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV2_GatePitches").toDouble(); 387 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV3_GatePitches").toDouble(); 388 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INV4_GatePitches").toDouble(); 389 area += gate_pitch * getTotalHeight() * getGenProperties()->get("INVZ1_GatePitches").toDouble(); 390 area [all...] |
/gem5/ext/mcpat/ |
H A D | core.cc | 124 IB->area.set_area(IB->area.get_area() + IB->local_result.area); 125 area.set_area(area.get_area() + IB->local_result.area); 173 area.set_area(area.get_area() + BTB->local_result.area); 177 area [all...] |
H A D | basic_components.cc | 57 area = 0.0; 67 to_return.area = lhs.area + rhs.area; 81 area += rhs.area; 151 area.set_area(0.0); 152 output_data.area = 0.0; 155 output_data.area += area [all...] |
H A D | interconnect.cc | 116 area.set_area(area.get_area()*data_width); 141 area.set_area(area.get_area() * route_over_perc + 160 area.set_area(wtemp1->area.get_area()); 193 output_data.area = area.get_area() / 1e6;
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H A D | logic.cc | 56 output_data.area = local_result.area; 264 area.set_area(5 * compute_gate_area(NAND, 2,WdecNANDn,WdecNANDp, 365 area.set_area(num_piperegs * pipe_reg.area.get_area()); 379 area.set_area(area.get_area() * macro_layout_overhead); 381 output_data.area = area.get_area() / 1e6; 616 area [all...] |
/gem5/src/base/ |
H A D | bmpwriter.cc | 60 const uint32_t pixel_array_size(sizeof(PixelType) * fb.area());
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