| /gem5/tests/configs/ |
| H A D | minor-timing-mp.py | 46 cpu_class=MinorCPU, num_cpus=nb_cores).create_root()
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| H A D | minor-timing.py | 45 cpu_class=MinorCPU).create_root()
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| H A D | realview-minor-dual.py | 43 cpu_class=MinorCPU,
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| H A D | realview-minor.py | 43 cpu_class=MinorCPU).create_root()
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| H A D | realview64-minor-dual.py | 44 cpu_class=MinorCPU,
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| H A D | realview64-minor.py | 44 cpu_class=MinorCPU).create_root()
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| H A D | tsunami-minor-dual.py | 43 cpu_class=MinorCPU,
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| H A D | tsunami-minor.py | 43 cpu_class=MinorCPU).create_root()
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| H A D | realview-switcheroo-full.py | 44 cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
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| H A D | realview64-switcheroo-full.py | 45 cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
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| /gem5/src/cpu/minor/ |
| H A D | cpu.cc | 47 #include "debug/MinorCPU.hh"
50 MinorCPU::MinorCPU(MinorCPUParams *params) : function in class:MinorCPU
84 MinorCPU::~MinorCPU()
94 MinorCPU::init()
126 MinorCPU::regStats()
134 MinorCPU::serializeThread(CheckpointOut &cp, ThreadID thread_id) const
140 MinorCPU::unserializeThread(CheckpointIn &cp, ThreadID thread_id)
146 MinorCPU
[all...] |
| H A D | pipeline.hh | 43 * The constructed pipeline. Kept out of MinorCPU to keep the interface
56 #include "params/MinorCPU.hh"
65 * Minor contains all the definitions within the MinorCPU apart from the CPU
69 /** The constructed pipeline. Kept out of MinorCPU to keep the interface
74 MinorCPU &cpu;
110 Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms);
138 MinorCPU::MinorCPUPort &getInstPort();
140 MinorCPU::MinorCPUPort &getDataPort();
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| H A D | cpu.hh | 54 #include "params/MinorCPU.hh"
67 * MinorCPU is an in-order CPU model with four fixed pipeline stages:
74 * This pipeline is carried in the MinorCPU::pipeline object.
75 * The exec_context interface is not carried by MinorCPU but by
79 class MinorCPU : public BaseCPU class in inherits:BaseCPU
88 * stages will access it through the CPU as the MinorCPU object
104 MinorCPU &cpu;
107 MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
123 MinorCPU(MinorCPUParams *params);
125 ~MinorCPU();
[all...] |
| H A D | fetch1.hh | 65 class IcachePort : public MinorCPU::MinorCPUPort
72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
73 MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
192 MinorCPU &cpu;
386 MinorCPU &cpu_,
395 MinorCPU::MinorCPUPort &getIcachePort() { return icachePort; }
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| H A D | decode.hh | 66 MinorCPU &cpu;
142 MinorCPU &cpu_,
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| H A D | pipeline.cc | 49 #include "debug/MinorCPU.hh"
56 Pipeline::Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms) :
186 MinorCPU::MinorCPUPort &
192 MinorCPU::MinorCPUPort &
207 DPRINTF(MinorCPU, "Draining pipeline by halting inst fetches. "
250 DPRINTF(MinorCPU, "Pipeline undrained stages state:%s%s%s%s%s%s%s%s\n",
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| H A D | execute.hh | 72 MinorCPU &cpu;
318 MinorCPU &cpu_,
328 MinorCPU::MinorCPUPort &getDcachePort();
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| H A D | lsq.hh | 65 MinorCPU &cpu;
89 class DcachePort : public MinorCPU::MinorCPUPort
96 DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
97 MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
643 MinorCPU &cpu_, Execute &execute_,
725 MinorCPU::MinorCPUPort &getDcachePort() { return dcachePort; }
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| H A D | fetch2.hh | 54 #include "params/MinorCPU.hh"
65 MinorCPU &cpu;
203 MinorCPU &cpu_,
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| H A D | decode.cc | 49 MinorCPU &cpu_,
110 MinorCPU &cpu)
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| H A D | MinorCPU.py | 188 class MinorCPU(BaseCPU): class in inherits:BaseCPU
189 type = 'MinorCPU'
291 print("Checker not yet supported by MinorCPU")
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| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 98 class ex5_LITTLE(MinorCPU):
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| /gem5/configs/example/arm/ |
| H A D | starter_fs.py | 76 "minor" : (MinorCPU,
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| H A D | starter_se.py | 70 "minor" : (MinorCPU,
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| /gem5/tests/gem5/cpu_tests/ |
| H A D | run.py | 105 'MinorCPU': MinorCPU,
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