110260SAndrew.Bardsley@arm.com# Copyright (c) 2013 ARM Limited
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1110260SAndrew.Bardsley@arm.com# modified or unmodified, in source code or in binary form.
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1310260SAndrew.Bardsley@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
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3810260SAndrew.Bardsley@arm.com#
3910260SAndrew.Bardsley@arm.com# Authors: Andreas Hansson
4010260SAndrew.Bardsley@arm.com
4110260SAndrew.Bardsley@arm.comfrom m5.objects import *
4210260SAndrew.Bardsley@arm.comfrom base_config import *
4310260SAndrew.Bardsley@arm.com
4410260SAndrew.Bardsley@arm.comnb_cores = 4
4511837Swendy.elsasser@arm.comroot = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
4610260SAndrew.Bardsley@arm.com                    cpu_class=MinorCPU, num_cpus=nb_cores).create_root()
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