Searched hist:13601 (Results 1 - 9 of 9) sorted by relevance
| /gem5/src/arch/generic/ | ||
| H A D | traits.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| /gem5/src/cpu/o3/ | ||
| H A D | rename_map.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | rename_map.cc | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | thread_context_impl.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | rename_impl.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | cpu.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | cpu.cc | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| /gem5/src/arch/arm/ | ||
| H A D | utility.cc | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
| H A D | isa.hh | 13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601 |
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