/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | ma_fetch.S | 7 # Test misaligned fetch trap. 29 # Without RVC, the jalr should trap, and the handler will skip ahead. 30 # With RVC, the jalr should not trap, and "j fail" should get skipped. 96 # Not-taken branches should not trap, even without RVC. 116 # tests 2, 4, 5, and 6 should trap 131 # verify trap cause
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H A D | scall.S | 7 # Test syscall trap. 29 # This is the expected trap code.
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H A D | sbreak.S | 7 # Test syscall trap.
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H A D | dirty.S | 63 # Make sure that superpage entries trap when PPN LSBs are set.
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | breakpoint.S | 16 # Set up breakpoint to trap on M-mode fetches. 43 # Make sure reads don't trap. 48 # Set up breakpoint to trap on M-mode reads. 63 # Make sure writes don't trap. 68 # Set up breakpoint to trap on M-mode stores. 121 # Only even-numbered tests should trap.
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H A D | illegal.S | 7 # Test illegal instruction trap. 60 # Make sure WFI doesn't trap when TW=0. 67 # Make sure WFI does trap when TW=1. 71 # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. 79 # Make sure SFENCE.VMA and sptbr do trap when TVM=1. 86 # Make sure SRET doesn't trap when TSR=0. 98 # Make sure SRET does trap when TSR=1.
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H A D | ma_addr.S | 7 # Test misaligned ld/st trap.
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/gem5/src/cpu/o3/ |
H A D | dyn_inst_impl.hh | 189 BaseO3DynInst<Impl>::trap(const Fault &fault) function in class:BaseO3DynInst 191 this->cpu->trap(fault, this->threadNumber, this->staticInst);
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H A D | dyn_inst.hh | 252 void trap(const Fault &fault);
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H A D | commit_impl.hh | 483 // Also check if any of the threads has a trap pending 530 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 532 EventFunctionWrapper *trap = new EventFunctionWrapper( local 539 cpu->schedule(trap, cpu->clockEdge(latency)); 596 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 776 // Generate trap squash event. 792 // Don't propagate intterupts if we are currently handling a trap or 1212 // Check if the instruction caused a fault. If so, trap. 1243 // Mark that we're in state update mode so that the trap's 1247 // Execute the trap [all...] |
H A D | cpu.hh | 275 * If a thread is trying to exit and its corresponding trap event 318 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
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H A D | cpu.cc | 907 this->trap(interrupt, 0, nullptr); 912 FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, function in class:FullO3CPU 1778 // exit trap event is processed in the future. Until then, it'll be still 1796 // exit trap event has been processed. Now, the thread is ready to exit
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/gem5/src/base/ |
H A D | remote_gdb.hh | 142 bool trap(int type); 143 bool breakpoint() { return trap(SIGTRAP); } 210 void process() { gdb->trap(_type); }
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H A D | remote_gdb.cc | 193 gdb->trap(SIGTRAP); 423 BaseRemoteGDB::trap(int type) function in class:BaseRemoteGDB 429 DPRINTF(GDBMisc, "trap: PC=%s\n", tc->pcState()); 435 * a breakpoint trap in kgdb_connect(), in which case we 500 warn("GDB trap event has already been scheduled!"); 676 trap(SIGTRAP);
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.cc | 779 bool trap = false; 786 trap = isWfe? !sctlr.ntwe : !sctlr.ntwi; 789 trap = isWfe? hcr.twe : hcr.twi; 792 trap = isWfe? scr.twe : scr.twi; 798 return trap; 810 // target exception level (where the trap will be handled) 816 // Check if processor needs to trap at selected exception level 817 bool trap = isWFxTrapping(tc, targetEL, isWfe); 819 if (trap) { 849 // Check if processor needs to trap a [all...] |
H A D | misc64.cc | 87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, function in class:MiscRegOp64 380 Fault fault = trap(tc, miscReg, el, imm);
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H A D | misc64.hh | 132 Fault trap(ThreadContext *tc, MiscRegIndex misc_reg,
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