112771Sqtt2@cornell.edu# See LICENSE for license details. 212771Sqtt2@cornell.edu 312771Sqtt2@cornell.edu#***************************************************************************** 412771Sqtt2@cornell.edu# breakpoint.S 512771Sqtt2@cornell.edu#----------------------------------------------------------------------------- 612771Sqtt2@cornell.edu# 712771Sqtt2@cornell.edu# Test breakpoints, if they are implemented. 812771Sqtt2@cornell.edu# 912771Sqtt2@cornell.edu 1012771Sqtt2@cornell.edu#include "riscv_test.h" 1112771Sqtt2@cornell.edu#include "test_macros.h" 1212771Sqtt2@cornell.edu 1312771Sqtt2@cornell.eduRVTEST_RV64M 1412771Sqtt2@cornell.eduRVTEST_CODE_BEGIN 1512771Sqtt2@cornell.edu 1612771Sqtt2@cornell.edu # Set up breakpoint to trap on M-mode fetches. 1712771Sqtt2@cornell.edu li TESTNUM, 2 1812771Sqtt2@cornell.edu 1912771Sqtt2@cornell.edu # Skip tselect if hard-wired. 2012771Sqtt2@cornell.edu csrw tselect, x0 2112771Sqtt2@cornell.edu csrr a1, tselect 2212771Sqtt2@cornell.edu bne x0, a1, pass 2312771Sqtt2@cornell.edu 2412771Sqtt2@cornell.edu # Make sure there's a breakpoint there. 2512771Sqtt2@cornell.edu csrr a0, tdata1 2612771Sqtt2@cornell.edu srli a0, a0, __riscv_xlen - 4 2712771Sqtt2@cornell.edu li a1, 2 2812771Sqtt2@cornell.edu bne a0, a1, pass 2912771Sqtt2@cornell.edu 3012771Sqtt2@cornell.edu la a2, 1f 3112771Sqtt2@cornell.edu csrw tdata2, a2 3212771Sqtt2@cornell.edu li a0, MCONTROL_M | MCONTROL_EXECUTE 3312771Sqtt2@cornell.edu csrw tdata1, a0 3412771Sqtt2@cornell.edu # Skip if breakpoint type is unsupported. 3512771Sqtt2@cornell.edu csrr a1, tdata1 3612771Sqtt2@cornell.edu andi a1, a1, 0x7ff 3712771Sqtt2@cornell.edu bne a0, a1, 2f 3812771Sqtt2@cornell.edu .align 2 3912771Sqtt2@cornell.edu1: 4012771Sqtt2@cornell.edu # Trap handler should skip this instruction. 4112771Sqtt2@cornell.edu beqz x0, fail 4212771Sqtt2@cornell.edu 4312771Sqtt2@cornell.edu # Make sure reads don't trap. 4412771Sqtt2@cornell.edu li TESTNUM, 3 4512771Sqtt2@cornell.edu lw a0, (a2) 4612771Sqtt2@cornell.edu 4712771Sqtt2@cornell.edu2: 4812771Sqtt2@cornell.edu # Set up breakpoint to trap on M-mode reads. 4912771Sqtt2@cornell.edu li TESTNUM, 4 5012771Sqtt2@cornell.edu li a0, MCONTROL_M | MCONTROL_LOAD 5112771Sqtt2@cornell.edu csrw tdata1, a0 5212771Sqtt2@cornell.edu # Skip if breakpoint type is unsupported. 5312771Sqtt2@cornell.edu csrr a1, tdata1 5412771Sqtt2@cornell.edu andi a1, a1, 0x7ff 5512771Sqtt2@cornell.edu bne a0, a1, 2f 5612771Sqtt2@cornell.edu la a2, data1 5712771Sqtt2@cornell.edu csrw tdata2, a2 5812771Sqtt2@cornell.edu 5912771Sqtt2@cornell.edu # Trap handler should skip this instruction. 6012771Sqtt2@cornell.edu lw a2, (a2) 6112771Sqtt2@cornell.edu beqz a2, fail 6212771Sqtt2@cornell.edu 6312771Sqtt2@cornell.edu # Make sure writes don't trap. 6412771Sqtt2@cornell.edu li TESTNUM, 5 6512771Sqtt2@cornell.edu sw x0, (a2) 6612771Sqtt2@cornell.edu 6712771Sqtt2@cornell.edu2: 6812771Sqtt2@cornell.edu # Set up breakpoint to trap on M-mode stores. 6912771Sqtt2@cornell.edu li TESTNUM, 6 7012771Sqtt2@cornell.edu li a0, MCONTROL_M | MCONTROL_STORE 7112771Sqtt2@cornell.edu csrw tdata1, a0 7212771Sqtt2@cornell.edu # Skip if breakpoint type is unsupported. 7312771Sqtt2@cornell.edu csrr a1, tdata1 7412771Sqtt2@cornell.edu andi a1, a1, 0x7ff 7512771Sqtt2@cornell.edu bne a0, a1, 2f 7612771Sqtt2@cornell.edu 7712771Sqtt2@cornell.edu # Trap handler should skip this instruction. 7812771Sqtt2@cornell.edu sw a2, (a2) 7912771Sqtt2@cornell.edu 8012771Sqtt2@cornell.edu # Make sure store didn't succeed. 8112771Sqtt2@cornell.edu li TESTNUM, 7 8212771Sqtt2@cornell.edu lw a2, (a2) 8312771Sqtt2@cornell.edu bnez a2, fail 8412771Sqtt2@cornell.edu 8512771Sqtt2@cornell.edu # Try to set up a second breakpoint. 8612771Sqtt2@cornell.edu li a0, 1 8712771Sqtt2@cornell.edu csrw tselect, a0 8812771Sqtt2@cornell.edu csrr a1, tselect 8912771Sqtt2@cornell.edu bne a0, a1, pass 9012771Sqtt2@cornell.edu 9112771Sqtt2@cornell.edu # Make sure there's a breakpoint there. 9212771Sqtt2@cornell.edu csrr a0, tdata1 9312771Sqtt2@cornell.edu srli a0, a0, __riscv_xlen - 4 9412771Sqtt2@cornell.edu li a1, 2 9512771Sqtt2@cornell.edu bne a0, a1, pass 9612771Sqtt2@cornell.edu 9712771Sqtt2@cornell.edu li a0, MCONTROL_M | MCONTROL_LOAD 9812771Sqtt2@cornell.edu csrw tdata1, a0 9912771Sqtt2@cornell.edu la a3, data2 10012771Sqtt2@cornell.edu csrw tdata2, a3 10112771Sqtt2@cornell.edu 10212771Sqtt2@cornell.edu # Make sure the second breakpoint triggers. 10312771Sqtt2@cornell.edu li TESTNUM, 8 10412771Sqtt2@cornell.edu lw a3, (a3) 10512771Sqtt2@cornell.edu beqz a3, fail 10612771Sqtt2@cornell.edu 10712771Sqtt2@cornell.edu # Make sure the first breakpoint still triggers. 10812771Sqtt2@cornell.edu li TESTNUM, 10 10912771Sqtt2@cornell.edu la a2, data1 11012771Sqtt2@cornell.edu sw a2, (a2) 11112771Sqtt2@cornell.edu li TESTNUM, 11 11212771Sqtt2@cornell.edu lw a2, (a2) 11312771Sqtt2@cornell.edu bnez a2, fail 11412771Sqtt2@cornell.edu 11512771Sqtt2@cornell.edu2: 11612771Sqtt2@cornell.edu TEST_PASSFAIL 11712771Sqtt2@cornell.edu 11812771Sqtt2@cornell.edu .align 2 11912771Sqtt2@cornell.edu .global mtvec_handler 12012771Sqtt2@cornell.edumtvec_handler: 12112771Sqtt2@cornell.edu # Only even-numbered tests should trap. 12212771Sqtt2@cornell.edu andi t0, TESTNUM, 1 12312771Sqtt2@cornell.edu bnez t0, fail 12412771Sqtt2@cornell.edu 12512771Sqtt2@cornell.edu li t0, CAUSE_BREAKPOINT 12612771Sqtt2@cornell.edu csrr t1, mcause 12712771Sqtt2@cornell.edu bne t0, t1, fail 12812771Sqtt2@cornell.edu 12912771Sqtt2@cornell.edu csrr t0, mepc 13012771Sqtt2@cornell.edu addi t0, t0, 4 13112771Sqtt2@cornell.edu csrw mepc, t0 13212771Sqtt2@cornell.edu mret 13312771Sqtt2@cornell.edu 13412771Sqtt2@cornell.eduRVTEST_CODE_END 13512771Sqtt2@cornell.edu 13612771Sqtt2@cornell.edu .data 13712771Sqtt2@cornell.eduRVTEST_DATA_BEGIN 13812771Sqtt2@cornell.edu 13912771Sqtt2@cornell.edu TEST_DATA 14012771Sqtt2@cornell.edu 14112771Sqtt2@cornell.edudata1: .word 0 14212771Sqtt2@cornell.edudata2: .word 0 14312771Sqtt2@cornell.edu 14412771Sqtt2@cornell.eduRVTEST_DATA_END 145