| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/ |
| H A D | jalr.S | 22 li t0, 0
25 jalr t0, t1, 0
31 bne t0, t1, fail
48 TEST_CASE( 7, t0, 4, \
49 li t0, 1; \
52 addi t0, t0, 1; \
53 addi t0, t0, 1; \
54 addi t0, t
[all...] |
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64uamt/ |
| H A D | amoor_d.S | 72 la t0, array_index
74 amoadd.d t1, t1, (t0) // get my array_index
76 la t0, array
77 add t0, t0, t1
78 ld t0, (t0) // get array[array_index]
80 amoor.d zero, t0, (a0)
82 li t0, 1
84 amoadd.d zero, t0, (a
[all...] |
| H A D | amoxor_d.S | 72 la t0, array_index
74 amoadd.d t1, t1, (t0) // get my array_index
76 la t0, array
77 add t0, t0, t1
78 ld t0, (t0) // get array[array_index]
80 amoxor.d zero, t0, (a0)
82 li t0, 1
84 amoadd.d zero, t0, (a
[all...] |
| H A D | amoand_d.S | 59 li t0, 0xffffffffffffffff
60 sd t0, (a0)
79 la t0, array_index
81 amoadd.d t1, t1, (t0) // get my array_index
83 la t0, array
84 add t0, t0, t1
85 ld t0, (t0) // get array[array_index]
87 amoand.d zero, t0, (a
[all...] |
| H A D | amomax_d.S | 59 li t0, 0x8000000000000000
60 sd t0, (a0)
79 la t0, array_index
81 amoadd.d t1, t1, (t0) // get my array_index
83 la t0, array
84 add t0, t0, t1
85 ld t0, (t0) // get array[array_index]
87 amomax.d zero, t0, (a
[all...] |
| H A D | amomaxu_d.S | 59 li t0, 0x0000000000000000
60 sd t0, (a0)
79 la t0, array_index
81 amoadd.d t1, t1, (t0) // get my array_index
83 la t0, array
84 add t0, t0, t1
85 ld t0, (t0) // get array[array_index]
87 amomaxu.d zero, t0, (a
[all...] |
| H A D | amomin_d.S | 59 li t0, 0x7fffffffffffffff
60 sd t0, (a0)
79 la t0, array_index
81 amoadd.d t1, t1, (t0) // get my array_index
83 la t0, array
84 add t0, t0, t1
85 ld t0, (t0) // get array[array_index]
87 amomin.d zero, t0, (a
[all...] |
| H A D | amominu_d.S | 59 li t0, 0xffffffffffffffff
60 sd t0, (a0)
79 la t0, array_index
81 amoadd.d t1, t1, (t0) // get my array_index
83 la t0, array
84 add t0, t0, t1
85 ld t0, (t0) // get array[array_index]
87 amominu.d zero, t0, (a
[all...] |
| H A D | amoadd_d.S | 74 li t0, 1 // one operand of amoadd_w
78 amoadd.d zero, t0, (a0)
83 amoadd.d zero, t0, (a0)
|
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
| H A D | dirty.S | 39 lw t0, dummy - DRAM_BASE
40 bnez t0, die
46 lw t0, dummy - DRAM_BASE
47 bne t0, t2, die
50 li t0, MSTATUS_MPRV
51 csrc mstatus, t0
54 lw t0, page_table_1
56 and t0, t0, a0
57 bne t0, a
[all...] |
| H A D | scall.S | 35 li t0, MSTATUS_MPP
36 csrc mstatus, t0
38 and t0, t0, t1
39 beqz t0, 1f
46 li t0, SSTATUS_SPP
47 csrc sstatus, t0
48 la t0, 1f
49 csrw sepc, t0
63 csrr t0, scaus
[all...] |
| H A D | csr.S | 32 li t0, MSTATUS_MPP
33 csrc mstatus, t0
35 and t0, t0, t1
36 bnez t0, 1f
86 li t0, SSTATUS_SPP
87 csrc sstatus, t0
88 la t0, 1f
89 csrw sepc, t0
118 li t0,
[all...] |
| H A D | sbreak.S | 37 csrr t0, scause
38 bne t0, t1, fail
40 csrr t0, sepc
41 bne t0, t1, fail
|
| H A D | ma_fetch.S | 33 la t0, 1f
34 jalr t1, t0, 2
46 la t0, 1f
47 jalr t1, t0, 1
55 la t0, 1f
56 jalr t1, t0, 3
69 la t0, 1f
84 la t0, 1f
136 # verify that epc == &jalr (== t0 - 4)
139 bne t0, a
[all...] |
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
| H A D | illegal.S | 25 li t0, MSTATUS_MPP
26 csrc mstatus, t0
30 and t2, t2, t0
37 la t0, mtvec_handler + 1
38 csrrw s0, mtvec, t0
39 csrr t0, mtvec
40 andi t0, t0, 1
41 beqz t0, msip
51 la t0,
[all...] |
| H A D | ma_addr.S | 98 csrr t0, mcause
99 bne t0, s1, fail
101 csrr t0, mbadaddr
102 bne t0, t1, fail
104 lb t0, (t0)
105 beqz t0, fail
|
| H A D | mcsr.S | 32 li t0, 0
33 csrs mtvec, t0
34 csrs mepc, t0
|
| /gem5/system/alpha/console/ |
| H A D | paljtokern.S | 68 lda t0, 0x1(zero)
69 sll t0, 33, t0
71 mtpr t0, mVptBr // Load Mbox copy
72 mtpr t0, iVptBr // Load Ibox copy
76 lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
78 mtpr t0, mcsr // Set the super page mode enable bit
81 lda t0, 0(zero)
82 mtpr t0, dtbAsn
83 mtpr t0, itbAs
[all...] |
| H A D | paljtoslave.S | 64 lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
66 mtpr t0, mcsr // Set the super page mode enable bit
69 lda t0, 0(zero)
70 mtpr t0, dtbAsn
71 mtpr t0, itbAsn
75 mfpr t0, icsr // Enable superpage mapping
77 bis t0, t1, t0
78 mtpr t0, icsr
|
| /gem5/tests/test-progs/asmtest/src/riscv/env/p/ |
| H A D | riscv_test.h | 57 la t0, 1f; \
58 csrw mtvec, t0; \
59 li t0, -1; /* Set up a PMP to permit all accesses */ \
60 csrw pmpaddr0, t0; \
61 li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
62 csrw pmpcfg0, t0; \
67 la t0, 1f; \
68 csrw mtvec, t0; \
74 la t0, 1f; \
75 csrw mtvec, t0; \
[all...] |
| /gem5/tests/test-progs/asmtest/src/riscv/env/ps/ |
| H A D | riscv_test.h | 57 la t0, 1f; \
58 csrw mtvec, t0; \
59 li t0, -1; /* Set up a PMP to permit all accesses */ \
60 csrw pmpaddr0, t0; \
61 li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
62 csrw pmpcfg0, t0; \
67 la t0, 1f; \
68 csrw mtvec, t0; \
74 la t0, 1f; \
75 csrw mtvec, t0; \
[all...] |
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64samt/ |
| H A D | sysfutex_d.S | 90 li t0, LOOP_COUNT
116 // decrement t0
117 addi t0, t0, -1
118 bnez t0, 1b
130 li t0, LOOP_COUNT
157 // decrement t0
158 addi t0, t0, -1
159 bnez t0,
[all...] |
| H A D | sysfutex3_d.S | 89 li t0, 0 // number of threads that have been waken
108 addi t0, t0, 1
122 add t0, t0, a0 // track the number of waken threads so far
131 add t0, t0, a0 // track the number of waken threads so far
134 blt t0, t1, 2b
|
| H A D | sysfutex2_d.S | 92 li t0, LOOP_COUNT
127 // decrement t0
128 addi t0, t0, -1
129 bnez t0, 1b
141 li t0, LOOP_COUNT
168 // decrement t0
169 addi t0, t0, -1
170 bnez t0,
[all...] |
| /gem5/tests/test-progs/asmtest/src/riscv/isa/macros/mt/ |
| H A D | test_macros_mt.h | 84 li t0, NUM_THREADS variable
91 addi t0, t0, -1 variable
92 bnez t0, 1b
120 la t0, barrier variable
123 ld t2, (t0)
131 li t0, NUM_THREADS variable
137 addi t0, t0, -1 variable
138 bnez t0,
[all...] |