112771Sqtt2@cornell.edu// See LICENSE for license details. 212771Sqtt2@cornell.edu 312771Sqtt2@cornell.edu#ifndef _ENV_PHYSICAL_SINGLE_CORE_H 412771Sqtt2@cornell.edu#define _ENV_PHYSICAL_SINGLE_CORE_H 512771Sqtt2@cornell.edu 612771Sqtt2@cornell.edu#include "../encoding.h" 712771Sqtt2@cornell.edu 812771Sqtt2@cornell.edu//----------------------------------------------------------------------- 912771Sqtt2@cornell.edu// Begin Macro 1012771Sqtt2@cornell.edu//----------------------------------------------------------------------- 1112771Sqtt2@cornell.edu 1212771Sqtt2@cornell.edu#define RVTEST_RV64U \ 1312771Sqtt2@cornell.edu .macro init; \ 1412771Sqtt2@cornell.edu .endm 1512771Sqtt2@cornell.edu 1612771Sqtt2@cornell.edu#define RVTEST_RV64UF \ 1712771Sqtt2@cornell.edu .macro init; \ 1812771Sqtt2@cornell.edu RVTEST_FP_ENABLE; \ 1912771Sqtt2@cornell.edu .endm 2012771Sqtt2@cornell.edu 2112771Sqtt2@cornell.edu#define RVTEST_RV32U \ 2212771Sqtt2@cornell.edu .macro init; \ 2312771Sqtt2@cornell.edu .endm 2412771Sqtt2@cornell.edu 2512771Sqtt2@cornell.edu#define RVTEST_RV32UF \ 2612771Sqtt2@cornell.edu .macro init; \ 2712771Sqtt2@cornell.edu RVTEST_FP_ENABLE; \ 2812771Sqtt2@cornell.edu .endm 2912771Sqtt2@cornell.edu 3012771Sqtt2@cornell.edu#define RVTEST_RV64M \ 3112771Sqtt2@cornell.edu .macro init; \ 3212771Sqtt2@cornell.edu RVTEST_ENABLE_MACHINE; \ 3312771Sqtt2@cornell.edu .endm 3412771Sqtt2@cornell.edu 3512771Sqtt2@cornell.edu#define RVTEST_RV64S \ 3612771Sqtt2@cornell.edu .macro init; \ 3712771Sqtt2@cornell.edu RVTEST_ENABLE_SUPERVISOR; \ 3812771Sqtt2@cornell.edu .endm 3912771Sqtt2@cornell.edu 4012771Sqtt2@cornell.edu#define RVTEST_RV32M \ 4112771Sqtt2@cornell.edu .macro init; \ 4212771Sqtt2@cornell.edu RVTEST_ENABLE_MACHINE; \ 4312771Sqtt2@cornell.edu .endm 4412771Sqtt2@cornell.edu 4512771Sqtt2@cornell.edu#define RVTEST_RV32S \ 4612771Sqtt2@cornell.edu .macro init; \ 4712771Sqtt2@cornell.edu RVTEST_ENABLE_SUPERVISOR; \ 4812771Sqtt2@cornell.edu .endm 4912771Sqtt2@cornell.edu 5012771Sqtt2@cornell.edu#if __riscv_xlen == 64 5112771Sqtt2@cornell.edu# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: 5212771Sqtt2@cornell.edu#else 5312771Sqtt2@cornell.edu# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: 5412771Sqtt2@cornell.edu#endif 5512771Sqtt2@cornell.edu 5612771Sqtt2@cornell.edu#define INIT_PMP \ 5712771Sqtt2@cornell.edu la t0, 1f; \ 5812771Sqtt2@cornell.edu csrw mtvec, t0; \ 5912771Sqtt2@cornell.edu li t0, -1; /* Set up a PMP to permit all accesses */ \ 6012771Sqtt2@cornell.edu csrw pmpaddr0, t0; \ 6112771Sqtt2@cornell.edu li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ 6212771Sqtt2@cornell.edu csrw pmpcfg0, t0; \ 6312771Sqtt2@cornell.edu .align 2; \ 6412771Sqtt2@cornell.edu1: 6512771Sqtt2@cornell.edu 6612771Sqtt2@cornell.edu#define INIT_SATP \ 6712771Sqtt2@cornell.edu la t0, 1f; \ 6812771Sqtt2@cornell.edu csrw mtvec, t0; \ 6912771Sqtt2@cornell.edu csrwi sptbr, 0; \ 7012771Sqtt2@cornell.edu .align 2; \ 7112771Sqtt2@cornell.edu1: 7212771Sqtt2@cornell.edu 7312771Sqtt2@cornell.edu#define DELEGATE_NO_TRAPS \ 7412771Sqtt2@cornell.edu la t0, 1f; \ 7512771Sqtt2@cornell.edu csrw mtvec, t0; \ 7612771Sqtt2@cornell.edu csrwi medeleg, 0; \ 7712771Sqtt2@cornell.edu csrwi mideleg, 0; \ 7812771Sqtt2@cornell.edu csrwi mie, 0; \ 7912771Sqtt2@cornell.edu .align 2; \ 8012771Sqtt2@cornell.edu1: 8112771Sqtt2@cornell.edu 8212771Sqtt2@cornell.edu#define RVTEST_ENABLE_SUPERVISOR \ 8312771Sqtt2@cornell.edu li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ 8412771Sqtt2@cornell.edu csrs mstatus, a0; \ 8512771Sqtt2@cornell.edu li a0, SIP_SSIP | SIP_STIP; \ 8612771Sqtt2@cornell.edu csrs mideleg, a0; \ 8712771Sqtt2@cornell.edu 8812771Sqtt2@cornell.edu#define RVTEST_ENABLE_MACHINE \ 8912771Sqtt2@cornell.edu li a0, MSTATUS_MPP; \ 9012771Sqtt2@cornell.edu csrs mstatus, a0; \ 9112771Sqtt2@cornell.edu 9212771Sqtt2@cornell.edu#define RVTEST_FP_ENABLE \ 9312771Sqtt2@cornell.edu li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ 9412771Sqtt2@cornell.edu csrs mstatus, a0; \ 9512771Sqtt2@cornell.edu csrwi fcsr, 0 9612771Sqtt2@cornell.edu 9712771Sqtt2@cornell.edu#define RISCV_MULTICORE_DISABLE \ 9812771Sqtt2@cornell.edu csrr a0, mhartid; \ 9912771Sqtt2@cornell.edu 1: bnez a0, 1b 10012771Sqtt2@cornell.edu 10112771Sqtt2@cornell.edu#define EXTRA_TVEC_USER 10212771Sqtt2@cornell.edu#define EXTRA_TVEC_MACHINE 10312771Sqtt2@cornell.edu#define EXTRA_INIT 10412771Sqtt2@cornell.edu#define EXTRA_INIT_TIMER 10512771Sqtt2@cornell.edu 10612771Sqtt2@cornell.edu#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ 10712771Sqtt2@cornell.edu 10812771Sqtt2@cornell.edu#define RVTEST_CODE_BEGIN \ 10912771Sqtt2@cornell.edu .section .text.init; \ 11012771Sqtt2@cornell.edu .align 6; \ 11112771Sqtt2@cornell.edu .weak stvec_handler; \ 11212771Sqtt2@cornell.edu .weak mtvec_handler; \ 11312771Sqtt2@cornell.edu .globl _start; \ 11412771Sqtt2@cornell.edu_start: \ 11512771Sqtt2@cornell.edu /* reset vector */ \ 11612771Sqtt2@cornell.edu j reset_vector; \ 11712771Sqtt2@cornell.edu .align 2; \ 11812771Sqtt2@cornell.edutrap_vector: \ 11912771Sqtt2@cornell.edu /* test whether the test came from pass/fail */ \ 12012771Sqtt2@cornell.edu csrr t5, mcause; \ 12112771Sqtt2@cornell.edu li t6, CAUSE_USER_ECALL; \ 12212771Sqtt2@cornell.edu beq t5, t6, write_tohost; \ 12312771Sqtt2@cornell.edu li t6, CAUSE_SUPERVISOR_ECALL; \ 12412771Sqtt2@cornell.edu beq t5, t6, write_tohost; \ 12512771Sqtt2@cornell.edu li t6, CAUSE_MACHINE_ECALL; \ 12612771Sqtt2@cornell.edu beq t5, t6, write_tohost; \ 12712771Sqtt2@cornell.edu /* if an mtvec_handler is defined, jump to it */ \ 12812771Sqtt2@cornell.edu la t5, mtvec_handler; \ 12912771Sqtt2@cornell.edu beqz t5, 1f; \ 13012771Sqtt2@cornell.edu jr t5; \ 13112771Sqtt2@cornell.edu /* was it an interrupt or an exception? */ \ 13212771Sqtt2@cornell.edu 1: csrr t5, mcause; \ 13312771Sqtt2@cornell.edu bgez t5, handle_exception; \ 13412771Sqtt2@cornell.edu INTERRUPT_HANDLER; \ 13512771Sqtt2@cornell.eduhandle_exception: \ 13612771Sqtt2@cornell.edu /* we don't know how to handle whatever the exception was */ \ 13712771Sqtt2@cornell.edu other_exception: \ 13812771Sqtt2@cornell.edu /* some unhandlable exception occurred */ \ 13912771Sqtt2@cornell.edu 1: ori TESTNUM, TESTNUM, 1337; \ 14012771Sqtt2@cornell.edu write_tohost: \ 14112771Sqtt2@cornell.edu sw TESTNUM, tohost, t5; \ 14212771Sqtt2@cornell.edu j write_tohost; \ 14312771Sqtt2@cornell.edureset_vector: \ 14412771Sqtt2@cornell.edu RISCV_MULTICORE_DISABLE; \ 14512771Sqtt2@cornell.edu INIT_SATP; \ 14612771Sqtt2@cornell.edu INIT_PMP; \ 14712771Sqtt2@cornell.edu DELEGATE_NO_TRAPS; \ 14812771Sqtt2@cornell.edu li TESTNUM, 0; \ 14912771Sqtt2@cornell.edu la t0, trap_vector; \ 15012771Sqtt2@cornell.edu csrw mtvec, t0; \ 15112771Sqtt2@cornell.edu CHECK_XLEN; \ 15212771Sqtt2@cornell.edu /* if an stvec_handler is defined, delegate exceptions to it */ \ 15312771Sqtt2@cornell.edu la t0, stvec_handler; \ 15412771Sqtt2@cornell.edu beqz t0, 1f; \ 15512771Sqtt2@cornell.edu csrw stvec, t0; \ 15612771Sqtt2@cornell.edu li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ 15712771Sqtt2@cornell.edu (1 << CAUSE_STORE_PAGE_FAULT) | \ 15812771Sqtt2@cornell.edu (1 << CAUSE_FETCH_PAGE_FAULT) | \ 15912771Sqtt2@cornell.edu (1 << CAUSE_MISALIGNED_FETCH) | \ 16012771Sqtt2@cornell.edu (1 << CAUSE_USER_ECALL) | \ 16112771Sqtt2@cornell.edu (1 << CAUSE_BREAKPOINT); \ 16212771Sqtt2@cornell.edu csrw medeleg, t0; \ 16312771Sqtt2@cornell.edu csrr t1, medeleg; \ 16412771Sqtt2@cornell.edu bne t0, t1, other_exception; \ 16512771Sqtt2@cornell.edu1: csrwi mstatus, 0; \ 16612771Sqtt2@cornell.edu init; \ 16712771Sqtt2@cornell.edu EXTRA_INIT; \ 16812771Sqtt2@cornell.edu EXTRA_INIT_TIMER; \ 16912771Sqtt2@cornell.edu la t0, 1f; \ 17012771Sqtt2@cornell.edu csrw mepc, t0; \ 17112771Sqtt2@cornell.edu csrr a0, mhartid; \ 17212771Sqtt2@cornell.edu mret; \ 17312771Sqtt2@cornell.edu1: 17412771Sqtt2@cornell.edu 17512771Sqtt2@cornell.edu//----------------------------------------------------------------------- 17612771Sqtt2@cornell.edu// End Macro 17712771Sqtt2@cornell.edu//----------------------------------------------------------------------- 17812771Sqtt2@cornell.edu 17912771Sqtt2@cornell.edu#define RVTEST_CODE_END \ 18012771Sqtt2@cornell.edu unimp 18112771Sqtt2@cornell.edu 18212771Sqtt2@cornell.edu//----------------------------------------------------------------------- 18312771Sqtt2@cornell.edu// Pass/Fail Macro 18412771Sqtt2@cornell.edu//----------------------------------------------------------------------- 18512771Sqtt2@cornell.edu 18612771Sqtt2@cornell.edu#define RVTEST_PASS \ 18712771Sqtt2@cornell.edu fence; \ 18812771Sqtt2@cornell.edu li TESTNUM, 1; \ 18912771Sqtt2@cornell.edu ecall 19012771Sqtt2@cornell.edu 19112771Sqtt2@cornell.edu#define TESTNUM gp 19212771Sqtt2@cornell.edu#define RVTEST_FAIL \ 19312771Sqtt2@cornell.edu fence; \ 19412771Sqtt2@cornell.edu1: beqz TESTNUM, 1b; \ 19512771Sqtt2@cornell.edu sll TESTNUM, TESTNUM, 1; \ 19612771Sqtt2@cornell.edu or TESTNUM, TESTNUM, 1; \ 19712771Sqtt2@cornell.edu ecall 19812771Sqtt2@cornell.edu 19912771Sqtt2@cornell.edu//----------------------------------------------------------------------- 20012771Sqtt2@cornell.edu// Data Section Macro 20112771Sqtt2@cornell.edu//----------------------------------------------------------------------- 20212771Sqtt2@cornell.edu 20312771Sqtt2@cornell.edu#define EXTRA_DATA 20412771Sqtt2@cornell.edu 20512771Sqtt2@cornell.edu#define RVTEST_DATA_BEGIN \ 20612771Sqtt2@cornell.edu EXTRA_DATA \ 20712771Sqtt2@cornell.edu .pushsection .tohost,"aw",@progbits; \ 20812771Sqtt2@cornell.edu .align 6; .global tohost; tohost: .dword 0; \ 20912771Sqtt2@cornell.edu .align 6; .global fromhost; fromhost: .dword 0; \ 21012771Sqtt2@cornell.edu .popsection; \ 21112771Sqtt2@cornell.edu .align 4; .global begin_signature; begin_signature: 21212771Sqtt2@cornell.edu 21312771Sqtt2@cornell.edu#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: 21412771Sqtt2@cornell.edu 21512771Sqtt2@cornell.edu#endif 216