18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 2003-2004 The Regents of The University of Michigan 38029Snate@binkert.org * Copyright (c) 1993 The Hewlett-Packard Development Company 48029Snate@binkert.org * All rights reserved. 58013Sbinkertn@umich.edu * 68029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 78029Snate@binkert.org * modification, are permitted provided that the following conditions are 88029Snate@binkert.org * met: redistributions of source code must retain the above copyright 98029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 108029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 118029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 128029Snate@binkert.org * documentation and/or other materials provided with the distribution; 138029Snate@binkert.org * neither the name of the copyright holders nor the names of its 148029Snate@binkert.org * contributors may be used to endorse or promote products derived from 158029Snate@binkert.org * this software without specific prior written permission. 168013Sbinkertn@umich.edu * 178029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288013Sbinkertn@umich.edu */ 298012Ssaidi@eecs.umich.edu 308013Sbinkertn@umich.edu#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 318013Sbinkertn@umich.edu#include "ev5_defs.h" 328013Sbinkertn@umich.edu#include "fromHudsonOsf.h" // OSF/1 specific definitions 338013Sbinkertn@umich.edu#include "fromHudsonMacros.h" // Global macro definitions 348012Ssaidi@eecs.umich.edu 358012Ssaidi@eecs.umich.edu/* 368013Sbinkertn@umich.edu * args: 378013Sbinkertn@umich.edu * a0: here 388013Sbinkertn@umich.edu * a1: boot location 398013Sbinkertn@umich.edu * a2: CSERVE_J_KTOPAL 408013Sbinkertn@umich.edu * a3: restrart_pv 418013Sbinkertn@umich.edu * a4: vptb 428013Sbinkertn@umich.edu * a5: my_rpb 438013Sbinkertn@umich.edu * 448013Sbinkertn@umich.edu * SRM Console Architecture III 3-26 458013Sbinkertn@umich.edu */ 468008Ssaidi@eecs.umich.edu 478008Ssaidi@eecs.umich.edu .global palJToSlave 488008Ssaidi@eecs.umich.edu .text 3 498008Ssaidi@eecs.umich.edupalJToSlave: 508008Ssaidi@eecs.umich.edu 518008Ssaidi@eecs.umich.edu ALIGN_BRANCH 528008Ssaidi@eecs.umich.edu 538008Ssaidi@eecs.umich.edu bis a3, zero, pv 548008Ssaidi@eecs.umich.edu bis zero, zero, t11 558008Ssaidi@eecs.umich.edu bis zero, zero, ra 568008Ssaidi@eecs.umich.edu 578008Ssaidi@eecs.umich.edu /* Point the Vptbr to a2 */ 588008Ssaidi@eecs.umich.edu 598008Ssaidi@eecs.umich.edu mtpr a4, mVptBr // Load Mbox copy 608008Ssaidi@eecs.umich.edu mtpr a4, iVptBr // Load Ibox copy 618008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 628008Ssaidi@eecs.umich.edu 638008Ssaidi@eecs.umich.edu /* Turn on superpage mapping in the mbox and icsr */ 648008Ssaidi@eecs.umich.edu lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 658008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 668013Sbinkertn@umich.edu mtpr t0, mcsr // Set the super page mode enable bit 678008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 688008Ssaidi@eecs.umich.edu 698008Ssaidi@eecs.umich.edu lda t0, 0(zero) 708008Ssaidi@eecs.umich.edu mtpr t0, dtbAsn 718008Ssaidi@eecs.umich.edu mtpr t0, itbAsn 728008Ssaidi@eecs.umich.edu 738008Ssaidi@eecs.umich.edu LDLI (t1,0x20000000) 748008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 758013Sbinkertn@umich.edu mfpr t0, icsr // Enable superpage mapping 768008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 778008Ssaidi@eecs.umich.edu bis t0, t1, t0 788008Ssaidi@eecs.umich.edu mtpr t0, icsr 798008Ssaidi@eecs.umich.edu 808013Sbinkertn@umich.edu STALL // Required stall to update chip ... 818008Ssaidi@eecs.umich.edu STALL 828008Ssaidi@eecs.umich.edu STALL 838008Ssaidi@eecs.umich.edu STALL 848008Ssaidi@eecs.umich.edu STALL 858008Ssaidi@eecs.umich.edu 868008Ssaidi@eecs.umich.edu ldq_p s0, PCB_Q_PTBR(a5) 878013Sbinkertn@umich.edu sll s0, VA_S_OFF, s0 // Shift PTBR into position 888008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 898013Sbinkertn@umich.edu mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 908008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 918008Ssaidi@eecs.umich.edu ldq_p sp, PCB_Q_KSP(a5) 928008Ssaidi@eecs.umich.edu 938013Sbinkertn@umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 948013Sbinkertn@umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 958008Ssaidi@eecs.umich.edu 968013Sbinkertn@umich.edu mtpr a1, excAddr // Load the dispatch address. 978008Ssaidi@eecs.umich.edu 988008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 998008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1008013Sbinkertn@umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1018013Sbinkertn@umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1028008Ssaidi@eecs.umich.edu br zero, 2f 1038008Ssaidi@eecs.umich.edu 1048008Ssaidi@eecs.umich.edu ALIGN_BLOCK 1058008Ssaidi@eecs.umich.edu 1068008Ssaidi@eecs.umich.edu2: NOP 1078013Sbinkertn@umich.edu mtpr zero, icFlush // Flush the icache. 1088008Ssaidi@eecs.umich.edu NOP 1098008Ssaidi@eecs.umich.edu NOP 1108008Ssaidi@eecs.umich.edu 1118013Sbinkertn@umich.edu NOP // Required NOPs ... 1-10 1128008Ssaidi@eecs.umich.edu NOP 1138008Ssaidi@eecs.umich.edu NOP 1148008Ssaidi@eecs.umich.edu NOP 1158008Ssaidi@eecs.umich.edu NOP 1168008Ssaidi@eecs.umich.edu NOP 1178008Ssaidi@eecs.umich.edu NOP 1188008Ssaidi@eecs.umich.edu NOP 1198008Ssaidi@eecs.umich.edu NOP 1208008Ssaidi@eecs.umich.edu NOP 1218008Ssaidi@eecs.umich.edu 1228013Sbinkertn@umich.edu NOP // Required NOPs ... 11-20 1238008Ssaidi@eecs.umich.edu NOP 1248008Ssaidi@eecs.umich.edu NOP 1258008Ssaidi@eecs.umich.edu NOP 1268008Ssaidi@eecs.umich.edu NOP 1278008Ssaidi@eecs.umich.edu NOP 1288008Ssaidi@eecs.umich.edu NOP 1298008Ssaidi@eecs.umich.edu NOP 1308008Ssaidi@eecs.umich.edu NOP 1318008Ssaidi@eecs.umich.edu NOP 1328008Ssaidi@eecs.umich.edu 1338013Sbinkertn@umich.edu NOP // Required NOPs ... 21-30 1348008Ssaidi@eecs.umich.edu NOP 1358008Ssaidi@eecs.umich.edu NOP 1368008Ssaidi@eecs.umich.edu NOP 1378008Ssaidi@eecs.umich.edu NOP 1388008Ssaidi@eecs.umich.edu NOP 1398008Ssaidi@eecs.umich.edu NOP 1408008Ssaidi@eecs.umich.edu NOP 1418008Ssaidi@eecs.umich.edu NOP 1428008Ssaidi@eecs.umich.edu NOP 1438008Ssaidi@eecs.umich.edu 1448013Sbinkertn@umich.edu NOP // Required NOPs ... 31-40 1458008Ssaidi@eecs.umich.edu NOP 1468008Ssaidi@eecs.umich.edu NOP 1478008Ssaidi@eecs.umich.edu NOP 1488008Ssaidi@eecs.umich.edu NOP 1498008Ssaidi@eecs.umich.edu NOP 1508008Ssaidi@eecs.umich.edu NOP 1518008Ssaidi@eecs.umich.edu NOP 1528008Ssaidi@eecs.umich.edu NOP 1538008Ssaidi@eecs.umich.edu NOP 1548008Ssaidi@eecs.umich.edu 1558013Sbinkertn@umich.edu NOP // Required NOPs ... 41-44 1568008Ssaidi@eecs.umich.edu NOP 1578008Ssaidi@eecs.umich.edu NOP 1588008Ssaidi@eecs.umich.edu NOP 1598008Ssaidi@eecs.umich.edu 1608013Sbinkertn@umich.edu hw_rei_stall // Dispatch to kernel 1618008Ssaidi@eecs.umich.edu 162