| /gem5/src/systemc/tests/systemc/misc/stars/star106015/ |
| H A D | mem.h | 38 struct memory : sc_module { struct in inherits:sc_module
45 SC_HAS_PROCESS( memory );
47 memory (const char *NAME) function in struct:memory
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| H A D | star106015.cpp | 41 void memory::entry(){
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| /gem5/src/sim/probe/ |
| H A D | pmu.hh | 42 #include <memory>
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| H A D | mem.hh | 42 #include <memory>
75 * want to instrument Packets in the memory system. Components should
80 * <li>PktRequest: Requests sent out on the memory side of a normal
85 * <li>PktResponse: Response received from the memory side of a
86 * normal component or a response being sent out from a memory.
88 * <li>PktRequestCPU: Incoming, accepted, memory request on the CPU
95 * <li>PktResponseCPU: Outgoing response memory request on the CPU
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| /gem5/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ |
| H A D | ram.cpp | 52 memory[address] = datain.read().to_int();
57 dataout.write(memory[address]);
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| H A D | ram.h | 56 int memory[4000]; local
59 const int wait_cycles; // Number of cycles it takes to access memory
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| /gem5/util/tlm/examples/slave_port/ |
| H A D | main.cc | 72 Target memory("memory",
77 memory.socket.bind(transactor.socket);
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| /gem5/src/mem/cache/replacement_policies/ |
| H A D | replaceable_entry.hh | 35 #include <memory>
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| H A D | base.hh | 34 #include <memory>
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| H A D | bip_rp.cc | 33 #include <memory>
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| H A D | tree_plru_rp.hh | 75 #include <memory>
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| /gem5/tests/test-progs/gpu-hello/bin/x86/linux/ |
| H A D | gpu-hello-kernel.asm | 4 %code_size %code_in %key_arr %msg_out %chars_decoded AMD RTI $ ARGSTART:__OpenCL_read_kernel_kernel $ , version:3:1:104 4 < device:generic D L
uniqueid:1024 T \ memory:private:0 d l memory:region:0 t | memory:local:16 � � ! value:__global_offset_0:u64:1:1:0 � � " value:__global_offset_1:u64:1:1:16 � � " value:__global_offset_2:u64:1:1:32 � � 2 pointer:__printf_buffer:u8:1:1:48:uav:7:1:RW:0:0:0 � � ! value:__vqueue_pointer:u64:1:1:64 � � " value:__aqlwrap_pointer:u64:1:1:80 � � value:code_size:u64:1:1:96 � � + pointer:code_in:u8:1:1:112:uav:7:1:RW:0:0:0 , pointer:key_arr:u32:1:1:128:uav:7:4:RW:0:0:0 + pointer:msg_out:u8:1:1:144:uav:7:1:RW:0:0:0 $ , 2 pointer:chars_decoded:u32:1:1:160:uav:7:4:RW:0:0:0 4 < function:1:0 D L memory:64bitABI T \ privateid:8 d l enqueue_kernel:0 t | kernel_index:0 � � reflection:0:size_t � � reflection:1:size_t � � reflection:2:size_t � � reflection:3:size_t � � reflection:4:size_t � � reflection:5:size_t � � reflection:6:size_t � � reflection:7:char* reflection:8:int* reflection:9:char* $ , reflection:10:int* 4 < " ARGEND:__OpenCL_read_kernel_kernel D L %read_kernel_lcount " @__OpenCL_read_kernel_kernel_entry // BB#0: T \ h p x � � � � � � � � � � � � , 4 H P X @BB0_2 d l // BB#1: t � � � � � � � � � � � � ( 0 8 @BB0_4 D L 6 // BB#3: // %.preheader T \ d l t | � � � � � � � � � � � � ( @BB0_5 0 8 @ H P ` @BB0_7 t | // BB#6: � � � � � � � hsa_code < H T ` ` ` ` | � � � � � � � � ( 4 @ � � � � ( H | � � ( \ � � � 4 p � � � , L p � � � $ H l � � � 0 X r l F x G � " � G � " � G � " u � G � " G � " E � T H � , W < " G @ T d G t E � T � � � � E 1 0 H @ + T J ` U x " � � H � l W � " T � � G � " M � I � J � � g � � $ hsa_operand 0T 0` 0T 0� 0T 0� 0T 0� 0T 0� 0T 0 0T 04 0T 0T 0T 0� 0T 0� 0T 0� 0T 04 0T 0h 0T 0� 0T 0� 0T 0 0T 0@ 0T 0| 0T 0� 0T 0� 0T 0� 0T 0 0T 08 0T 0X 0T 0| 0T 0� 0T 0� 0T 0� 0T 0 0T 00 0T 0T 0T 0x 0T 0� 0T 0� 0T 0�
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| /gem5/src/systemc/tests/systemc/misc/stars/star110069/ |
| H A D | mem0.h | 60 int* memory; local
87 memory (MEMORY)
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| H A D | star110069.cpp | 67 tmp2 = memory[tmp1];
68 cout << "memory content " << tmp2 << endl;
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| /gem5/src/arch/riscv/insts/ |
| H A D | unknown.hh | 35 #include <memory>
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| /gem5/src/mem/ |
| H A D | simple_mem.cc | 118 "Should only see read and writes at memory controller, "
135 // and since this is a memory controller we also need to
143 // limited for any real memory
172 // address, the latter is important as this memory effectively
267 : SlavePort(_name, &_memory), memory(_memory)
274 ranges.push_back(memory.getAddrRange());
281 return memory.recvAtomic(pkt);
288 return memory.recvAtomicBackdoor(pkt, _backdoor);
294 memory.recvFunctional(pkt);
300 return memory
[all...] |
| H A D | dram_ctrl.cc | 131 // if actual DRAM size does not match memory capacity in system warn!
243 // remember the memory system mode of operation
272 // do the actual memory access and turn the packet into a response
575 // we do not wait for the writes to be send to the actual memory,
626 "Should only see read and writes at memory controller\n");
922 // do the actual memory access which also turns the packet into a
1723 : EventManager(&_memory), memory(_memory),
1786 bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0))
1787 || ((memory.busStateNext == WRITE) &&
1821 divCeil(cmd.timeStamp, memory
[all...] |
| /gem5/src/mem/probes/ |
| H A D | base.hh | 43 #include <memory>
52 * Base class for memory system probes accepting Packet instances.
54 * This is a helper base class for memory system probes that
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| /gem5/src/dev/net/ |
| H A D | etherpkt.hh | 41 #include <memory>
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | Controller.py | 72 memory = MasterPort("Port for attaching a memory controller") variable in class:RubyController
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| /gem5/util/tlm/ |
| H A D | run_gem5_fs.sh | 40 --tlm-memory=transactor \
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| /gem5/src/mem/qos/ |
| H A D | mem_sink.cc | 127 "read and writes at memory controller\n",
272 "corresponds to %d memory packets\n", __func__, pkt->getAddr(),
280 // Do the actual memory access which also turns the packet
347 : QueuedSlavePort(n, &m, queue, true), memory(m), queue(memory, *this, true)
354 ranges.push_back(memory.getAddrRange());
361 return memory.recvAtomic(pkt);
367 pkt->pushLabel(memory.name());
373 memory.recvFunctional(pkt);
382 return memory
[all...] |
| /gem5/src/gpu-compute/ |
| H A D | kernel_cfg.hh | 41 #include <memory>
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| /gem5/src/arch/sparc/insts/ |
| H A D | unimp.hh | 34 #include <memory>
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| /gem5/src/base/ |
| H A D | compiler.hh | 46 #include <memory>
|