1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
33#define __ARCH_RISCV_UNKNOWN_INST_HH__
34
35#include <memory>
36#include <string>
37
38#include "arch/riscv/faults.hh"
39#include "arch/riscv/insts/bitfields.hh"
40#include "arch/riscv/insts/static_inst.hh"
41#include "cpu/exec_context.hh"
42#include "cpu/static_inst.hh"
43
44namespace RiscvISA
45{
46
47/**
48 * Static instruction class for unknown (illegal) instructions.
49 * These cause simulator termination if they are executed in a
50 * non-speculative mode.  This is a leaf class.
51 */
52class Unknown : public RiscvStaticInst
53{
54  public:
55    Unknown(MachInst _machInst)
56        : RiscvStaticInst("unknown", _machInst, No_OpClass)
57    {}
58
59    Fault
60    execute(ExecContext *, Trace::InstRecord *) const override
61    {
62        return std::make_shared<UnknownInstFault>(machInst);
63    }
64
65    std::string
66    generateDisassembly(Addr pc, const SymbolTable *symtab) const override
67    {
68        return csprintf("unknown opcode %#02x", OPCODE);
69    }
70};
71
72}
73
74#endif // __ARCH_RISCV_UNKNOWN_INST_HH__