src/mem/dram_ctrl.cc

131     // if actual DRAM size does not match memory capacity in system warn!
243     // remember the memory system mode of operation
272     // do the actual memory access and turn the packet into a response
575     // we do not wait for the writes to be send to the actual memory,
626              "Should only see read and writes at memory controller\n");
922     // do the actual memory access which also turns the packet into a
1723     : EventManager(&_memory), memory(_memory),
1786     bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0))
1787                           || ((memory.busStateNext == WRITE) &&
1821                                       divCeil(cmd.timeStamp, memory.tCK) -
1822                                       memory.timeStampOffset);
1860             memory.enableDRAMPowerdown) {
1911         if ((rank == memory.activeRank)
1912             && (memory.nextReqEvent.scheduled())) {
1930             scheduleWakeUpEvent(memory.tXP);
1957             Tick act_allowed_at = pre_at + memory.tRP;
1961                     memory.prechargeBank(*this, b, pre_at, false);
1972                     divCeil(pre_at, memory.tCK) -
1973                             memory.timeStampOffset, rank);
2005         Tick ref_done_at = curTick() + memory.tRFC;
2017         DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) -
2018                 memory.timeStampOffset, rank);
2021         refreshDueAt += memory.tREFI;
2043         if ((memory.drainState() == DrainState::Draining) ||
2044             (memory.drainState() == DrainState::Drained)) {
2061             } else if (isQueueEmpty() && memory.enableDRAMPowerdown) {
2082         schedule(refreshEvent, refreshDueAt - memory.tRP);
2121                 memory.tCK) - memory.timeStampOffset, rank);
2130                 memory.tCK) - memory.timeStampOffset, rank);
2140                 memory.tCK) - memory.timeStampOffset, rank);
2150                 memory.tCK) - memory.timeStampOffset, rank);
2155     wakeUpAllowedAt = tick + memory.tCK;
2200                 memory.tCK) - memory.timeStampOffset, rank);
2205                 memory.tCK) - memory.timeStampOffset, rank);
2209                 memory.tCK) - memory.timeStampOffset, rank);
2269         if (!memory.nextReqEvent.scheduled()) {
2272             schedule(memory.nextReqEvent, curTick());
2291             schedule(refreshEvent, curTick() + memory.tXS);
2307                         schedulePowerEvent(PWR_REF, curTick() + memory.tXP);
2328         // bypass auto-refresh and go straight to SREF, where memory
2331            (memory.drainState() != DrainState::Draining) &&
2332            (memory.drainState() != DrainState::Drained) &&
2333            memory.enableDRAMPowerdown) {
2375     power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) -
2376                                     memory.timeStampOffset);
2383     actEnergy += energy.act_energy * memory.devicesPerRank;
2384     preEnergy += energy.pre_energy * memory.devicesPerRank;
2385     readEnergy += energy.read_energy * memory.devicesPerRank;
2386     writeEnergy += energy.write_energy * memory.devicesPerRank;
2387     refreshEnergy += energy.ref_energy * memory.devicesPerRank;
2388     actBackEnergy += energy.act_stdby_energy * memory.devicesPerRank;
2389     preBackEnergy += energy.pre_stdby_energy * memory.devicesPerRank;
2390     actPowerDownEnergy += energy.f_act_pd_energy * memory.devicesPerRank;
2391     prePowerDownEnergy += energy.f_pre_pd_energy * memory.devicesPerRank;
2392     selfRefreshEnergy += energy.sref_energy * memory.devicesPerRank;
2395     totalEnergy += energy.window_energy * memory.devicesPerRank;
2403                     (curTick() - memory.lastStatsResetTick)) *
2426     power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) -
2427                                     memory.timeStampOffset);
2592         .desc("Average memory access latency per DRAM burst")
2760     // per-master bytes read and written to memory
2764         .desc("Per-master bytes read from memory")
2770         .desc("Per-master bytes write to memory")
2773     // per-master bytes read and written to memory rate
2775         .desc("Per-master bytes read from memory rate (Bytes/sec)")
2783         .desc("Per-master bytes write to memory rate (Bytes/sec)")
2792         .desc("Per-master read serviced memory accesses")
2798         .desc("Per-master write serviced memory accesses")
2805         .desc("Per-master read total memory access latency")
2809         .desc("Per-master read average memory access latency")
2818         .desc("Per-master write total memory access latency")
2822         .desc("Per-master write average memory access latency")
2846     // rely on the abstract memory
2930       memory(_memory)
2937     ranges.push_back(memory.getAddrRange());
2944     pkt->pushLabel(memory.name());
2950         memory.recvFunctional(pkt);
2959     return memory.recvAtomic(pkt);
2965     // pass it to the memory controller
2966     return memory.recvTimingReq(pkt);