| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | dram_rot_gen.cc | 64 isRead = !isRead;
68 isRead = readPercent != 0;
71 assert((readPercent == 0 && !isRead) ||
72 (readPercent == 100 && isRead) ||
125 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
129 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
|
| H A D | linear_gen.cc | 63 bool isRead = readPercent != 0 && local
66 assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead) ||
70 isRead ? 'r' : 'w', nextAddr, blocksize);
76 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
|
| H A D | random_gen.cc | 62 bool isRead = readPercent != 0 && local
65 assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead) ||
75 isRead ? 'r' : 'w', addr, blocksize);
82 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
|
| H A D | dram_gen.cc | 67 isRead(true), pageSize(page_size),
96 isRead = readPercent != 0 &&
99 assert((readPercent == 0 && !isRead) ||
100 (readPercent == 100 && isRead) ||
137 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
141 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
|
| H A D | dram_gen.hh | 123 bool isRead; member in class:DramGen
|
| H A D | trace_gen.cc | 146 currElement.cmd.isRead() ? 'r' : 'w',
158 nextElement.cmd.isRead() ? 'r' : 'w',
|
| /gem5/src/mem/probes/ |
| H A D | stack_dist.cc | 103 if (!pkt_info.cmd.isRead() && !pkt_info.cmd.isWrite())
118 if (pkt_info.cmd.isRead())
128 if (pkt_info.cmd.isRead())
|
| /gem5/src/arch/arm/ |
| H A D | utility.hh | 273 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, argument
276 return (isRead << 0) |
285 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, argument
288 isRead = (iss >> 0) & 0x1;
297 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, argument
300 return (isRead << 0) |
308 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, argument
311 return isRead |
|
| H A D | utility.cc | 464 bool isRead; local
480 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
576 trapToHype = hcr.tvm & !isRead;
605 bool isRead; local
614 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
660 bool isRead; local
667 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
688 trapToHype = hcr.tvm & !isRead;
|
| /gem5/src/mem/cache/ |
| H A D | noncoherent_cache.cc | 78 assert(pkt->isRead() || pkt->isWrite());
143 panic_if(!(pkt->isRead() || pkt->isWrite()),
187 assert(bus_pkt->isRead());
228 panic_if(!(pkt->isRead() || pkt->isWrite()),
326 assert(pkt->isRead());
|
| H A D | cache.cc | 86 if (pkt->isRead()) {
342 assert(pkt->isRead());
633 } else if (bus_pkt->isRead() ||
809 if (pkt->isRead() && !is_error) {
941 pkt = new Packet(req_pkt, false, req_pkt->isRead());
946 if (pkt->isRead()) {
1108 if (pkt->isRead() && !invalidate) {
1162 if (compressor && pkt->isRead()) {
1263 if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) {
|
| /gem5/util/tlm/src/ |
| H A D | sc_slave_port.cc | 71 if (packet->isRead()) {
95 panic_if(!(packet->isRead() || packet->isWrite()),
114 } else if (packet->isRead()) {
183 panic_if(!(packet->isRead() || packet->isWrite()),
|
| /gem5/src/arch/generic/ |
| H A D | mmapped_ipr.cc | 51 if (pkt->isRead())
|
| /gem5/src/mem/qos/ |
| H A D | mem_sink.cc | 125 panic_if(!(pkt->isRead() || pkt->isWrite()),
148 if (pkt->isRead()) {
180 logRequest(pkt->isRead()? READ : WRITE,
285 logResponse(pkt->isRead()? READ : WRITE,
|
| /gem5/src/dev/ |
| H A D | io_device.hh | 78 pkt->isRead() ? device->read(pkt) : device->write(pkt);
|
| /gem5/src/mem/ |
| H A D | mem_delay.cc | 182 if (pkt->isRead()) {
194 if (pkt->isRead()) {
|
| H A D | comm_monitor.cc | 250 if (pkt_info.cmd.isRead()) {
316 if (pkt_info.cmd.isRead()) {
405 DPRINTF(CommMonitor, "Forwarded %s request\n", pkt->isRead() ? "read" :
454 DPRINTF(CommMonitor, "Received %s response\n", pkt->isRead() ? "read" :
|
| H A D | mem_checker_monitor.cc | 145 bool is_read = pkt->isRead() && !pkt->req->isPrefetch();
234 bool is_read = pkt->isRead() && !pkt->req->isPrefetch();
|
| H A D | packet.hh | 199 bool isRead() const { return testCmdAttrib(IsRead); } function in class:MemCmd
530 bool isRead() const { return cmd.isRead(); } function
789 assert(isRead());
|
| H A D | simple_mem.cc | 117 panic_if(!(pkt->isRead() || pkt->isWrite()),
|
| H A D | dram_ctrl.cc | 307 bool isRead) const
407 return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
625 panic_if(!(pkt->isRead() || pkt->isWrite()),
661 assert(pkt->isRead());
840 const Tick col_allowed_at = dram_pkt->isRead() ? bank.rdAllowedAt :
1146 const Tick col_allowed_at = dram_pkt->isRead() ?
1173 dly_to_rd_cmd = dram_pkt->isRead() ?
1175 dly_to_wr_cmd = dram_pkt->isRead() ?
1180 dly_to_rd_cmd = dram_pkt->isRead() ? tBURST : wrToRdDly;
1181 dly_to_wr_cmd = dram_pkt->isRead()
[all...] |
| /gem5/src/dev/arm/ |
| H A D | smmu_v3_ports.cc | 130 return pkt->isRead() ? smmu.readControl(pkt) : smmu.writeControl(pkt);
|
| /gem5/src/systemc/tlm_bridge/ |
| H A D | gem5_to_tlm.cc | 106 } else if (packet->isRead()) {
289 panic_if(!(packet->isRead() || packet->isWrite()),
|
| /gem5/src/learning_gem5/part2/ |
| H A D | simple_cache.cc | 315 if (pkt->isWrite() || pkt->isRead()) {
348 } else if (pkt->isRead()) {
|
| /gem5/src/mem/ruby/system/ |
| H A D | Sequencer.cc | 553 assert(pkt->isRead());
569 assert(pkt->isRead());
577 // both isWrite() and isRead() are true, check isWrite() first here.
584 } else if (pkt->isRead()) {
|