Searched refs:fatal (Results 1 - 25 of 220) sorted by relevance

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/gem5/src/arch/riscv/
H A Didle_event.cc43 fatal("Idle Start Event Not Defined for RISCV ISA ");
H A Dvtophys.hh51 fatal("VTOPHYS: Unimplemented on RISC-V\n");
58 fatal("VTOPHYS: Unimplemented on RISC-V\n");
/gem5/src/arch/mips/
H A Didle_event.cc43 fatal("Idle Start Event Not Defined for MIPS ISA ");
H A Dvtophys.cc49 fatal("VTOPHYS: Unimplemented on MIPS\n");
56 fatal("VTOPHYS: Unimplemented on MIPS\n");
H A Dinterrupts.hh115 fatal("Serialization of Interrupts Unimplemented for MIPS");
121 fatal("Unserialization of Interrupts Unimplemented for MIPS");
/gem5/src/arch/power/
H A Dvtophys.cc38 fatal("vtophys: Unimplemented on POWER\n");
44 fatal("vtophys: Unimplemented on POWER\n");
H A Disa.hh67 fatal("Power does not currently have any misc regs defined\n");
74 fatal("Power does not currently have any misc regs defined\n");
81 fatal("Power does not currently have any misc regs defined\n");
87 fatal("Power does not currently have any misc regs defined\n");
/gem5/src/arch/hsail/
H A Dgpu_isa.hh58 fatal("HSAIL does not implement misc registers yet\n");
64 fatal("HSAIL does not implement misc registers yet\n");
/gem5/src/cpu/simple/
H A Dnoncaching.cc51 fatal("The direct CPU requires the memory system to be in the "
72 fatal("only one workload allowed");
/gem5/src/cpu/o3/
H A Dderiv.cc46 fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
49 fatal("Must specify at least one workload!");
/gem5/src/sim/
H A DRoot.py33 from m5.util import fatal
41 fatal("Attempt to allocate multiple instances of Root.")
/gem5/configs/common/
H A DSimpleOpts.py43 # For fatal
58 m5.fatal("Duplicate option: %s" % str(args))
61 m5.fatal("Can't add an option after calling SimpleOpts.parse_args")
/gem5/tests/
H A Drun.py80 def require_sim_object(name, fatal=False):
87 fatal -- Set to True to indicate that the test should fail
95 if fatal:
96 m5.fatal(msg)
101 def require_file(path, fatal=False, mode=os.F_OK):
108 fatal -- Set to True to indicate that the test should fail
123 if fatal:
124 m5.fatal(msg)
128 def require_kvm(kvm_dev="/dev/kvm", fatal=False):
133 fatal
[all...]
/gem5/src/gpu-compute/
H A Dscheduler.cc50 fatal("Unimplemented scheduling policy.\n");
/gem5/src/mem/
H A Dexternal_master.cc74 fatal("Can't find port handler type '%s'\n", portType);
80 fatal("%s: Can't find external port type: %s"
94 fatal("ExternalMaster %s: externalPort not set!\n", name());
96 fatal("ExternalMaster %s is unconnected!\n", name());
H A Ddramsim2_wrapper.cc90 fatal("DRAMSim2 wrapper failed to get clock\n");
98 fatal("DRAMSim2 wrapper failed to get queue size\n");
110 fatal("DRAMSim22 wrapper failed to get burst size\n");
128 fatal("DRAMSim2 wrapper could not open %s for reading\n", file_name);
145 fatal("DRAMSim2 wrapper could not find %s in %s\n", field_name,
/gem5/src/cpu/
H A Dnativetrace.cc46 fatal("All listeners are disabled!");
/gem5/src/dev/serial/
H A Dserial.cc62 fatal("A UART has already been associated with this device.\n");
/gem5/tests/quick/se/04.gpu/
H A Dtest.py44 fatal("Can't locate kernel code (.asm) in " + kernel_path)
/gem5/src/systemc/core/
H A Dsc_main_fiber.cc76 fatal("sc_main called but not defined.\n");
/gem5/src/arch/riscv/bare_metal/
H A Dsystem.cc40 fatal("Could not load bootloader file %s", p->bootloader);
/gem5/src/dev/net/
H A Detherint.cc41 fatal("Attempt to bind port %s to non-ethernet port %s.",
/gem5/src/cpu/testers/traffic_gen/
H A Dbase_gen.cc96 fatal("TrafficGen %s block size (%d) is larger than "
101 fatal("%s cannot have more than 100% reads", name());
104 fatal("%s cannot have min_period > max_period", name());
/gem5/ext/sst/
H A DExtMaster.cc47 #ifdef fatal // gem5 sets this
48 #undef fatal macro
124 out.fatal(CALL_INFO, 1, "received Event during Construction phase\n");
129 out.fatal(CALL_INFO, 1, "Can't handle non-MemEvent Event's\n");
156 out.fatal(CALL_INFO, 1, "Don't know how to convert "
191 out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase traffic\n");
197 out.fatal(CALL_INFO, 1, "gem5 senderState corrupt\n");
/gem5/src/arch/sparc/
H A Dsystem.cc59 fatal("Could not load reset binary %s", params()->reset_bin);
64 fatal("Could not load openboot bianry %s", params()->openboot_bin);
69 fatal("Could not load hypervisor binary %s", params()->hypervisor_bin);
74 fatal("Could not load nvram image %s", params()->nvram_bin);
79 fatal("Could not load hypervisor description image %s",
85 fatal("Could not load partition description image %s",

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