1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#include <cassert>
41
42/**
43 * When building the debug binary, we need to undo the command-line
44 * definition of DEBUG not to clash with DRAMSim2 print macros that
45 * are included for no obvious reason.
46 */
47#ifdef DEBUG
48#undef DEBUG
49#endif
50
51#include "mem/dramsim2_wrapper.hh"
52
53#include <fstream>
54
55#include "DRAMSim2/MultiChannelMemorySystem.h"
56#include "base/compiler.hh"
57#include "base/logging.hh"
58
59/**
60 * DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in
61 * the DRAMSim2 print macros), otherwise we get linking errors due to
62 * undefined references
63 */
64int SHOW_SIM_OUTPUT = 0;
65
66DRAMSim2Wrapper::DRAMSim2Wrapper(const std::string& config_file,
67                                 const std::string& system_file,
68                                 const std::string& working_dir,
69                                 const std::string& trace_file,
70                                 unsigned int memory_size_mb,
71                                 bool enable_debug) :
72    dramsim(new DRAMSim::MultiChannelMemorySystem(config_file, system_file,
73                                                  working_dir, trace_file,
74                                                  memory_size_mb, NULL, NULL)),
75    _clockPeriod(0.0), _queueSize(0), _burstSize(0)
76{
77    // tell DRAMSim2 to ignore its internal notion of a CPU frequency
78    dramsim->setCPUClockSpeed(0);
79
80    // switch on debug output if requested
81    if (enable_debug)
82        SHOW_SIM_OUTPUT = 1;
83
84    // there is no way of getting DRAMSim2 to tell us what frequency
85    // it is assuming, so we have to extract it ourselves
86    _clockPeriod = extractConfig<double>("tCK=",
87                                         working_dir + '/' + config_file);
88
89    if (!_clockPeriod)
90        fatal("DRAMSim2 wrapper failed to get clock\n");
91
92    // we also need to know what transaction queue size DRAMSim2 is
93    // using so we can stall when responses are blocked
94   _queueSize = extractConfig<unsigned int>("TRANS_QUEUE_DEPTH=",
95                                            working_dir + '/' + system_file);
96
97    if (!_queueSize)
98        fatal("DRAMSim2 wrapper failed to get queue size\n");
99
100
101   // finally, get the data bus bits and burst length so we can add a
102   // sanity check for the burst size
103    unsigned int dataBusBits =
104        extractConfig<unsigned int>("JEDEC_DATA_BUS_BITS=",
105                                    working_dir + '/' + system_file);
106   unsigned int burstLength =
107       extractConfig<unsigned int>("BL=", working_dir + '/' + config_file);
108
109   if (!dataBusBits || !burstLength)
110       fatal("DRAMSim22 wrapper failed to get burst size\n");
111
112   _burstSize = dataBusBits * burstLength / 8;
113}
114
115DRAMSim2Wrapper::~DRAMSim2Wrapper()
116{
117    delete dramsim;
118}
119
120template <typename T>
121T
122DRAMSim2Wrapper::extractConfig(const std::string& field_name,
123                               const std::string& file_name) const
124{
125    std::ifstream file_stream(file_name.c_str(), ios::in);
126
127    if (!file_stream.good())
128        fatal("DRAMSim2 wrapper could not open %s for reading\n", file_name);
129
130    bool found = false;
131    T res;
132    std::string line;
133    while (!found && file_stream) {
134        getline(file_stream, line);
135        if (line.substr(0, field_name.size()) == field_name) {
136            found = true;
137            istringstream iss(line.substr(field_name.size()));
138            iss >> res;
139        }
140    }
141
142    file_stream.close();
143
144    if (!found)
145        fatal("DRAMSim2 wrapper could not find %s in %s\n", field_name,
146              file_name);
147
148    return res;
149}
150
151void
152DRAMSim2Wrapper::printStats()
153{
154    dramsim->printStats(true);
155}
156
157void
158DRAMSim2Wrapper::setCallbacks(DRAMSim::TransactionCompleteCB* read_callback,
159                              DRAMSim::TransactionCompleteCB* write_callback)
160{
161    // simply pass it on, for now we ignore the power callback
162    dramsim->RegisterCallbacks(read_callback, write_callback, NULL);
163}
164
165bool
166DRAMSim2Wrapper::canAccept() const
167{
168    return dramsim->willAcceptTransaction();
169}
170
171void
172DRAMSim2Wrapper::enqueue(bool is_write, uint64_t addr)
173{
174    bool success M5_VAR_USED = dramsim->addTransaction(is_write, addr);
175    assert(success);
176}
177
178double
179DRAMSim2Wrapper::clockPeriod() const
180{
181    return _clockPeriod;
182}
183
184unsigned int
185DRAMSim2Wrapper::queueSize() const
186{
187    return _queueSize;
188}
189
190unsigned int
191DRAMSim2Wrapper::burstSize() const
192{
193    return _burstSize;
194}
195
196void
197DRAMSim2Wrapper::tick()
198{
199    dramsim->update();
200}
201