Searched refs:curCycle (Results 1 - 25 of 27) sorted by relevance

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/gem5/src/mem/ruby/network/garnet2.0/
H A DCrossbarSwitch.cc79 m_router->get_id(), m_router->curCycle());
82 if (!m_switch_buffer[inport]->isReady(m_router->curCycle()))
86 if (t_flit->is_stage(ST_, m_router->curCycle())) {
90 t_flit->advance_stage(LT_, m_router->curCycle() + Cycles(1));
91 t_flit->set_time(m_router->curCycle() + Cycles(1));
H A DOutputUnit.cc70 m_router->get_id(), m_id, out_vc, m_router->curCycle());
80 m_router->get_id(), m_id, out_vc, m_router->curCycle());
91 assert(m_outvc_state[out_vc]->isInState(ACTIVE_, m_router->curCycle()));
102 if (is_vc_idle(vc, m_router->curCycle()))
115 if (is_vc_idle(vc, m_router->curCycle())) {
116 m_outvc_state[vc]->setState(ACTIVE_, m_router->curCycle());
135 if (m_credit_link->isReady(m_router->curCycle())) {
140 set_vc_state(IDLE_, t_credit->get_vc(), m_router->curCycle());
H A DInputUnit.cc88 if (m_in_link->isReady(m_router->curCycle())) {
98 set_vc_active(vc, m_router->curCycle());
127 t_flit->advance_stage(SA_, m_router->curCycle());
134 t_flit->advance_stage(SA_, m_router->curCycle() + wait_time);
H A DNetworkInterface.cc152 Cycles dest_queueing_delay = (curCycle() - t_flit->get_dequeue_time());
182 "woke up at time: %lld\n", m_id, m_router_id, curCycle());
211 if (inNetLink->isReady(curCycle())) {
214 t_flit->set_dequeue_time(curCycle());
254 if (inCreditLink->isReady(curCycle())) {
258 m_out_vc_state[t_credit->get_vc()]->setState(IDLE_, curCycle());
276 Credit *credit_flit = new Credit(t_flit->get_vc(), is_free, curCycle());
392 curCycle());
394 fl->set_src_delay(curCycle() - ticksToCycles(msg_ptr->getTime()));
398 m_ni_out_vcs_enqueue_time[vc] = curCycle();
[all...]
H A DSwitchAllocator.cc122 m_router->curCycle())) {
207 m_router->curCycle());
225 t_flit->advance_stage(ST_, m_router->curCycle());
234 m_router->curCycle())));
238 m_router->curCycle());
243 m_router->curCycle());
248 m_router->curCycle());
328 m_router->curCycle()) &&
358 Cycles nextCycle = m_router->curCycle() + Cycles(1);
H A DNetworkLink.cc68 if (link_srcQueue->isReady(curCycle())) {
70 t_flit->set_time(curCycle() + m_latency);
/gem5/src/sim/
H A Dticked_object.hh120 return object.curCycle() - lastStopped;
127 lastStopped = object.curCycle();
H A Dclocked_object.hh198 curCycle() const function in class:Clocked
/gem5/src/cpu/minor/
H A Dfunc_unit.cc172 if (nextInsertCycle == 0 || timeSource.curCycle() > nextInsertCycle)
175 return nextInsertCycle - timeSource.curCycle();
181 return nextInsertCycle == 0 || timeSource.curCycle() >= nextInsertCycle;
192 if (nextInsertCycle <= timeSource.curCycle()) {
193 nextInsertCycle = timeSource.curCycle() + description.issueLat;
H A Dexecute.cc627 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
676 cpu.curCycle(), cpu.getContext(thread_id)))
755 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
1027 Cycles now = cpu.curCycle();
1268 inst->minimumCommitCycle = cpu.curCycle() +
1534 NULL, NULL, cpu.curCycle() + Cycles(1),
/gem5/src/arch/riscv/
H A Disa.cc120 tc->getCpuPtr()->curCycle());
121 return tc->getCpuPtr()->curCycle();
157 misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
158 return tc->getCpuPtr()->curCycle();
/gem5/src/mem/ruby/network/simple/
H A DThrottle.cc117 m_ruby_system->curCycle());
236 double time_delta = double(m_ruby_system->curCycle() -
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.cc226 m_last_progress_vector[proc] = curCycle();
240 check_ptr->performCallback(proc, data, curCycle());
264 Cycles current_time = curCycle();
/gem5/src/mem/ruby/system/
H A DSequencer.cc85 Cycles current_time = curCycle();
209 i->second = new SequencerRequest(pkt, request_type, curCycle());
229 i->second = new SequencerRequest(pkt, request_type, curCycle());
452 assert(curCycle() >= issued_time);
453 Cycles total_latency = curCycle() - issued_time;
458 firstResponseTime, curCycle());
H A DGPUCoalescer.cc158 Cycles current_time = curCycle();
347 curCycle());
363 curCycle());
1189 Cycles completion_time = curCycle();
H A DRubySystem.cc395 m_start_cycle = curCycle();
/gem5/src/gpu-compute/
H A Dshader.hh94 Tick curCycle() const { return curTick() / clock; } function in class:Shader
H A Dtlb_coalescer.hh152 Tick curCycle() const { return curTick() / clock; } function in class:TLBCoalescer
H A Dgpu_tlb.hh91 Tick curCycle() const { return curTick() / clock; } function in class:X86ISA::GpuTLB
/gem5/src/cpu/
H A Dbase.hh563 uint32_t delta = curCycle() - previousCycle;
583 previousCycle = curCycle();
/gem5/src/mem/ruby/structures/
H A DPrefetcher.cc255 stream->m_use_time = m_controller->curCycle();
297 mystream->m_use_time = m_controller->curCycle();
/gem5/src/arch/x86/
H A Disa.cc142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
309 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
/gem5/src/cpu/o3/
H A Dcpu.cc142 lastRunningCycle(curCycle())
571 lastRunningCycle = curCycle();
574 lastRunningCycle = curCycle();
721 Cycles cycles(curCycle() - lastRunningCycle);
747 lastRunningCycle = curCycle();
1153 lastRunningCycle = curCycle();
1708 Cycles cycles(curCycle() - lastRunningCycle);
/gem5/src/mem/cache/
H A Dbase.hh1139 blockedCycle = curCycle();
1159 blocked_cycles[cause] += curCycle() - blockedCycle;
/gem5/src/arch/alpha/
H A Dev5.cc165 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);

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