/gem5/src/systemc/tests/systemc/misc/sim_tests/tri_state2/ |
H A D | driver.cpp | 45 control.write(true); 50 control.write(false); 54 control.write(true); 59 control.write(false);
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H A D | ts_buf.h | 48 sc_in<bool> control; local 59 control(CONTROL); 61 sensitive << in << control; local
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H A D | main.cpp | 48 sc_signal<bool> control; local 53 driver D("Driver", clock, bus, control, out); 54 ts_buf B("Buffer", out, control, bus);
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H A D | driver.h | 50 sc_out<bool> control; local 62 control(CONTROL);
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H A D | ts_buf.cpp | 49 c = control.read();
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/gem5/src/systemc/tests/systemc/misc/user_guide/chpt6.1/ |
H A D | driver.cpp | 45 control.write(true); 50 control.write(false); 54 control.write(true); 59 control.write(false);
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H A D | main.cpp | 47 sc_signal<bool> control; local 52 driver D("Driver", clock, bus, control, out); 53 ts_buf B("Buffer", out, control, bus);
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H A D | ts_buf.h | 48 const sc_signal<bool>& control; //input local 56 : in(IN_), control(CONTROL), ts_out(TS_OUT) 60 sensitive << control; local
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H A D | driver.h | 50 sc_signal<bool>& control; //output local 59 : in(IN_), control(CONTROL), out(OUT_)
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H A D | ts_buf.cpp | 49 c = control.read();
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/gem5/src/dev/arm/ |
H A D | timer_a9global.cc | 60 : _name(__name), parent(_parent), intNum(int_num), control(0x0), 84 return ticks / parent->clockPeriod() / (control.prescalar + 1) - 1; 106 pkt->setLE<uint32_t>(control); 113 cmpValEvent.when(), parent->clockPeriod(), control.prescalar); 124 cmpValEvent.when(), parent->clockPeriod(), control.prescalar); 177 old_enable = control.enable; 178 old_cmpEnable = control.cmpEnable; 179 control = pkt->getLE<uint32_t>(); 180 if ((old_enable == 0) && control.enable) 182 if ((old_cmpEnable == 0) && control [all...] |
H A D | timer_sp804.cc | 58 : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20), 93 zeroEvent.when(), clock, control.timerPrescale); 96 time = time / clock / power(16, control.timerPrescale); 101 pkt->setLE<uint32_t>(control); 153 old_enable = control.timerEnable; 154 control = pkt->getLE<uint32_t>(); 155 if ((old_enable == 0) && control.timerEnable) 179 if (!control.timerEnable) 182 Tick time = clock * power(16, control.timerPrescale); 183 if (control [all...] |
H A D | kmi.cc | 55 : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0), 73 DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control); 74 data = control; 182 control = ctrl; 188 rawInterrupts, control, getInterrupt()); 192 rawInterrupts, control, getInterrupt()); 202 tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable; 203 tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable; 211 paramOut(cp, "ctrlreg", control); 220 paramIn(cp, "ctrlreg", control); [all...] |
H A D | kmi.hh | 77 /** control register 79 ControlReg control; member in class:Pl050 116 * Update the status of the interrupt and control registers and 121 void setInterrupts(InterruptReg ints) { updateIntCtrl(ints, control); }
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H A D | pl011.cc | 59 control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), 111 data = control; 218 control = data; 305 SERIALIZE_SCALAR(control); 321 UNSERIALIZE_SCALAR(control);
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H A D | timer_a9global.hh | 97 CTRL control; member in class:A9GlobalTimer::Timer
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H A D | timer_sp804.hh | 92 CTRL control; member in class:Sp804::Timer
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H A D | SMMUv3.py | 83 control = SlavePort('Control port for accessing memory-mapped registers') variable in class:SMMUv3 85 reg_map = Param.AddrRange('Address range for control registers') 197 self.control = bus.master
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/gem5/util/tlm/src/ |
H A D | sc_slave_port.hh | 126 Gem5SimControl& control; member in class:Gem5SystemC::SCSlavePortHandler 129 SCSlavePortHandler(Gem5SimControl& control) : control(control) {} argument
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H A D | sc_master_port.hh | 149 Gem5SimControl& control; member in class:Gem5SystemC::SCMasterPortHandler 152 SCMasterPortHandler(Gem5SimControl& control) : control(control) {} argument
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/late_reset_bug/ |
H A D | late_reset_bug.cpp | 41 SC_THREAD(control); 57 void control() function in struct:Top
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/living_dead_bug/ |
H A D | living_dead_bug.cpp | 41 SC_THREAD(control); 53 void control() function in struct:Top
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/recursive_kill_bug/ |
H A D | recursive_kill_bug.cpp | 41 SC_THREAD(control); 76 void control() function in struct:Top
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/disable_enable/ |
H A D | disable_enable.cpp | 45 SC_THREAD(control); 57 void control() function in struct:Top
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/gem5/src/systemc/tests/systemc/misc/stars/star110089/ |
H A D | star110089.cpp | 55 w_ctr writes to the control I/O port. We want to observe this, so added 58 Want to observe successive values on the control port, so added a wait() after 128 sc_out<char> control; /* printer control port */ local 250 #define w_ctr(dev,val) (control = (val))
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