1/*
2 * Copyright (c) 2010, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: William Wang
41 */
42
43
44/** @file
45 * Implementiation of a PL050 KMI
46 */
47
48#ifndef __DEV_ARM_PL050_HH__
49#define __DEV_ARM_PL050_HH__
50
51#include <list>
52
53#include "base/vnc/vncinput.hh"
54#include "dev/arm/amba_device.hh"
55#include "params/Pl050.hh"
56
57class PS2Device;
58
59class Pl050 : public AmbaIntDevice
60{
61  protected:
62    static const int kmiCr       = 0x000;
63    static const int kmiStat     = 0x004;
64    static const int kmiData     = 0x008;
65    static const int kmiClkDiv   = 0x00C;
66    static const int kmiISR      = 0x010;
67
68    BitUnion8(ControlReg)
69        Bitfield<0> force_clock_low;
70        Bitfield<1> force_data_low;
71        Bitfield<2> enable;
72        Bitfield<3> txint_enable;
73        Bitfield<4> rxint_enable;
74        Bitfield<5> type;
75    EndBitUnion(ControlReg)
76
77    /** control register
78     */
79    ControlReg control;
80
81    /** KMI status register */
82    BitUnion8(StatusReg)
83        Bitfield<0> data_in;
84        Bitfield<1> clk_in;
85        Bitfield<2> rxparity;
86        Bitfield<3> rxbusy;
87        Bitfield<4> rxfull;
88        Bitfield<5> txbusy;
89        Bitfield<6> txempty;
90    EndBitUnion(StatusReg)
91
92    StatusReg status;
93
94    /** clock divisor register
95     * This register is just kept around to satisfy reads after driver does
96     * writes. The divsor does nothing, as we're not actually signaling ps2
97     * serial commands to anything.
98     */
99    uint8_t clkdiv;
100
101    BitUnion8(InterruptReg)
102        Bitfield<0> rx;
103        Bitfield<1> tx;
104    EndBitUnion(InterruptReg)
105
106    /** raw interrupt register (unmasked) */
107    InterruptReg rawInterrupts;
108
109    /** Set or clear the TX interrupt */
110    void setTxInt(bool value);
111
112    /** Update the RX interrupt using PS/2 device state */
113    void updateRxInt();
114
115    /**
116     * Update the status of the interrupt and control registers and
117     * deliver an interrupt if required.
118     */
119    void updateIntCtrl(InterruptReg ints, ControlReg ctrl);
120
121    void setInterrupts(InterruptReg ints) { updateIntCtrl(ints, control); }
122    void setControl(ControlReg ctrl) { updateIntCtrl(rawInterrupts, ctrl); }
123
124    /** Get current interrupt value */
125    InterruptReg getInterrupt() const;
126
127    /** PS2 device connected to this KMI interface */
128    PS2Device *ps2;
129
130  public:
131    Pl050(const Pl050Params *p);
132
133    Tick read(PacketPtr pkt) override;
134    Tick write(PacketPtr pkt) override;
135
136    void serialize(CheckpointOut &cp) const override;
137    void unserialize(CheckpointIn &cp) override;
138};
139
140#endif // __DEV_ARM_PL050_HH__
141