17754SWilliam.Wang@arm.com/*
212659Sandreas.sandberg@arm.com * Copyright (c) 2010, 2017-2018 ARM Limited
37754SWilliam.Wang@arm.com * All rights reserved
47754SWilliam.Wang@arm.com *
57754SWilliam.Wang@arm.com * The license below extends only to copyright in the software and shall
67754SWilliam.Wang@arm.com * not be construed as granting a license to any other intellectual
77754SWilliam.Wang@arm.com * property including but not limited to intellectual property relating
87754SWilliam.Wang@arm.com * to a hardware implementation of the functionality of the software
97754SWilliam.Wang@arm.com * licensed hereunder.  You may use the software subject to the license
107754SWilliam.Wang@arm.com * terms below provided that you ensure that this notice is replicated
117754SWilliam.Wang@arm.com * unmodified and in its entirety in all distributions of the software,
127754SWilliam.Wang@arm.com * modified or unmodified, in source code or in binary form.
137754SWilliam.Wang@arm.com *
147754SWilliam.Wang@arm.com * Copyright (c) 2005 The Regents of The University of Michigan
157754SWilliam.Wang@arm.com * All rights reserved.
167754SWilliam.Wang@arm.com *
177754SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without
187754SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are
197754SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright
207754SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer;
217754SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright
227754SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the
237754SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution;
247754SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its
257754SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from
267754SWilliam.Wang@arm.com * this software without specific prior written permission.
277754SWilliam.Wang@arm.com *
287754SWilliam.Wang@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
297754SWilliam.Wang@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
307754SWilliam.Wang@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
317754SWilliam.Wang@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
327754SWilliam.Wang@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
337754SWilliam.Wang@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
347754SWilliam.Wang@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
357754SWilliam.Wang@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
367754SWilliam.Wang@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
377754SWilliam.Wang@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
387754SWilliam.Wang@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
397754SWilliam.Wang@arm.com *
407754SWilliam.Wang@arm.com * Authors: William Wang
417754SWilliam.Wang@arm.com */
427754SWilliam.Wang@arm.com
437754SWilliam.Wang@arm.com
447754SWilliam.Wang@arm.com/** @file
457754SWilliam.Wang@arm.com * Implementiation of a PL050 KMI
467754SWilliam.Wang@arm.com */
477754SWilliam.Wang@arm.com
487754SWilliam.Wang@arm.com#ifndef __DEV_ARM_PL050_HH__
497754SWilliam.Wang@arm.com#define __DEV_ARM_PL050_HH__
507754SWilliam.Wang@arm.com
517950SAli.Saidi@ARM.com#include <list>
527950SAli.Saidi@ARM.com
539330Schander.sudanthi@arm.com#include "base/vnc/vncinput.hh"
547950SAli.Saidi@ARM.com#include "dev/arm/amba_device.hh"
557754SWilliam.Wang@arm.com#include "params/Pl050.hh"
567754SWilliam.Wang@arm.com
5712659Sandreas.sandberg@arm.comclass PS2Device;
5812659Sandreas.sandberg@arm.com
5912659Sandreas.sandberg@arm.comclass Pl050 : public AmbaIntDevice
607754SWilliam.Wang@arm.com{
617754SWilliam.Wang@arm.com  protected:
627754SWilliam.Wang@arm.com    static const int kmiCr       = 0x000;
637754SWilliam.Wang@arm.com    static const int kmiStat     = 0x004;
647754SWilliam.Wang@arm.com    static const int kmiData     = 0x008;
657754SWilliam.Wang@arm.com    static const int kmiClkDiv   = 0x00C;
667754SWilliam.Wang@arm.com    static const int kmiISR      = 0x010;
677754SWilliam.Wang@arm.com
687950SAli.Saidi@ARM.com    BitUnion8(ControlReg)
697950SAli.Saidi@ARM.com        Bitfield<0> force_clock_low;
707950SAli.Saidi@ARM.com        Bitfield<1> force_data_low;
717950SAli.Saidi@ARM.com        Bitfield<2> enable;
727950SAli.Saidi@ARM.com        Bitfield<3> txint_enable;
737950SAli.Saidi@ARM.com        Bitfield<4> rxint_enable;
747950SAli.Saidi@ARM.com        Bitfield<5> type;
757950SAli.Saidi@ARM.com    EndBitUnion(ControlReg)
767754SWilliam.Wang@arm.com
777950SAli.Saidi@ARM.com    /** control register
787950SAli.Saidi@ARM.com     */
797950SAli.Saidi@ARM.com    ControlReg control;
807754SWilliam.Wang@arm.com
817950SAli.Saidi@ARM.com    /** KMI status register */
827950SAli.Saidi@ARM.com    BitUnion8(StatusReg)
837950SAli.Saidi@ARM.com        Bitfield<0> data_in;
847950SAli.Saidi@ARM.com        Bitfield<1> clk_in;
857950SAli.Saidi@ARM.com        Bitfield<2> rxparity;
867950SAli.Saidi@ARM.com        Bitfield<3> rxbusy;
877950SAli.Saidi@ARM.com        Bitfield<4> rxfull;
887950SAli.Saidi@ARM.com        Bitfield<5> txbusy;
897950SAli.Saidi@ARM.com        Bitfield<6> txempty;
907950SAli.Saidi@ARM.com    EndBitUnion(StatusReg)
917754SWilliam.Wang@arm.com
927950SAli.Saidi@ARM.com    StatusReg status;
937950SAli.Saidi@ARM.com
947950SAli.Saidi@ARM.com    /** clock divisor register
957950SAli.Saidi@ARM.com     * This register is just kept around to satisfy reads after driver does
967950SAli.Saidi@ARM.com     * writes. The divsor does nothing, as we're not actually signaling ps2
977950SAli.Saidi@ARM.com     * serial commands to anything.
987950SAli.Saidi@ARM.com     */
997754SWilliam.Wang@arm.com    uint8_t clkdiv;
1007754SWilliam.Wang@arm.com
1017950SAli.Saidi@ARM.com    BitUnion8(InterruptReg)
1027950SAli.Saidi@ARM.com        Bitfield<0> rx;
1037950SAli.Saidi@ARM.com        Bitfield<1> tx;
1047950SAli.Saidi@ARM.com    EndBitUnion(InterruptReg)
1057754SWilliam.Wang@arm.com
1067950SAli.Saidi@ARM.com    /** raw interrupt register (unmasked) */
1077950SAli.Saidi@ARM.com    InterruptReg rawInterrupts;
1087754SWilliam.Wang@arm.com
10912664Sandreas.sandberg@arm.com    /** Set or clear the TX interrupt */
11012664Sandreas.sandberg@arm.com    void setTxInt(bool value);
1117754SWilliam.Wang@arm.com
11212664Sandreas.sandberg@arm.com    /** Update the RX interrupt using PS/2 device state */
11312664Sandreas.sandberg@arm.com    void updateRxInt();
1147754SWilliam.Wang@arm.com
11512664Sandreas.sandberg@arm.com    /**
11612664Sandreas.sandberg@arm.com     * Update the status of the interrupt and control registers and
11712664Sandreas.sandberg@arm.com     * deliver an interrupt if required.
11812664Sandreas.sandberg@arm.com     */
11912664Sandreas.sandberg@arm.com    void updateIntCtrl(InterruptReg ints, ControlReg ctrl);
12012664Sandreas.sandberg@arm.com
12112664Sandreas.sandberg@arm.com    void setInterrupts(InterruptReg ints) { updateIntCtrl(ints, control); }
12212664Sandreas.sandberg@arm.com    void setControl(ControlReg ctrl) { updateIntCtrl(rawInterrupts, ctrl); }
12312664Sandreas.sandberg@arm.com
12412664Sandreas.sandberg@arm.com    /** Get current interrupt value */
12512659Sandreas.sandberg@arm.com    InterruptReg getInterrupt() const;
12612659Sandreas.sandberg@arm.com
12712659Sandreas.sandberg@arm.com    /** PS2 device connected to this KMI interface */
12812659Sandreas.sandberg@arm.com    PS2Device *ps2;
1297950SAli.Saidi@ARM.com
1307754SWilliam.Wang@arm.com  public:
13112659Sandreas.sandberg@arm.com    Pl050(const Pl050Params *p);
1327754SWilliam.Wang@arm.com
13311174Sandreas.hansson@arm.com    Tick read(PacketPtr pkt) override;
13411174Sandreas.hansson@arm.com    Tick write(PacketPtr pkt) override;
1357754SWilliam.Wang@arm.com
13611168Sandreas.hansson@arm.com    void serialize(CheckpointOut &cp) const override;
13711168Sandreas.hansson@arm.com    void unserialize(CheckpointIn &cp) override;
1387754SWilliam.Wang@arm.com};
1397754SWilliam.Wang@arm.com
1407950SAli.Saidi@ARM.com#endif // __DEV_ARM_PL050_HH__
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