Searched refs:VecRegRenameMode (Results 1 - 8 of 8) sorted by relevance

/gem5/src/arch/generic/
H A Dtraits.hh46 #include "enums/VecRegRenameMode.hh"
56 static Enums::VecRegRenameMode init(const ISA*) { return Enums::Full; }
58 static Enums::VecRegRenameMode
H A DISACommon.py42 class VecRegRenameMode(Enum): class in inherits:Enum
50 __all__ = ['VecRegRenameMode']
/gem5/src/arch/arm/
H A DArmISA.py45 from m5.objects.ISACommon import VecRegRenameMode
H A Disa.hh54 #include "enums/VecRegRenameMode.hh"
74 const Enums::VecRegRenameMode _vecRegRenameMode;
745 Enums::VecRegRenameMode
765 static Enums::VecRegRenameMode
771 static Enums::VecRegRenameMode
H A Disa.cc110 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
/gem5/src/cpu/o3/
H A Dcpu.hh367 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
370 void vecRenameMode(Enums::VecRegRenameMode vec_mode)
575 Enums::VecRegRenameMode vecMode;
H A Drename_map.hh57 #include "enums/VecRegRenameMode.hh"
195 using VecMode = Enums::VecRegRenameMode;
H A Dregfile.hh56 #include "enums/VecRegRenameMode.hh"
70 using VecMode = Enums::VecRegRenameMode;

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