xref: /gem5/src/arch/generic/ISACommon.py

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# Authors: Rekai Gonzalez

from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject

class VecRegRenameMode(Enum):
    '''Enum for Rename Mode in rename map
        Elem: Each native-elem in a vector register is renamed independently.
        Full: Vectors are renamed as one unit.'''

    vals = ['Full', 'Elem']


__all__ = ['VecRegRenameMode']