Searched refs:MemCtrl (Results 1 - 11 of 11) sorted by relevance

/gem5/src/mem/qos/
H A Dturnaround_policy.hh64 void setMemCtrl(MemCtrl* mem) { memCtrl = mem; };
71 virtual MemCtrl::BusState selectBusState() = 0;
75 MemCtrl* memCtrl;
H A Dturnaround_policy_ideal.cc53 MemCtrl::BusState
77 bus_state = MemCtrl::WRITE;
79 bus_state = MemCtrl::READ;
82 bus_state = ((memCtrl->getBusState() == MemCtrl::READ) ?
83 MemCtrl::WRITE : MemCtrl::READ);
92 (bus_state == MemCtrl::READ)? "READ" : "WRITE");
H A Dturnaround_policy_ideal.hh67 virtual MemCtrl::BusState selectBusState() override;
H A Dmem_ctrl.cc46 MemCtrl::MemCtrl(const QoSMemCtrlParams * p) function in class:QoS::MemCtrl
77 MemCtrl::~MemCtrl()
81 MemCtrl::init()
87 MemCtrl::logRequest(BusState dir, MasterID m_id, uint8_t qos,
144 MemCtrl::logResponse(BusState dir, MasterID m_id, uint8_t qos,
213 MemCtrl::schedule(MasterID m_id, uint64_t data)
227 MemCtrl::schedule(const PacketPtr pkt)
241 MemCtrl
[all...]
H A Dpolicy.hh74 void setMemCtrl(MemCtrl* mem) { memCtrl = mem; };
110 MemCtrl* memCtrl;
H A Dq_policy.hh51 class MemCtrl;
70 * @param p QoS::MemCtrl parameter variable
100 void setMemCtrl(MemCtrl* mem) { memCtrl = mem; };
110 MemCtrl* memCtrl;
H A Dmem_ctrl.hh57 * The QoS::MemCtrl is a base class for Memory objects
61 class MemCtrl: public AbstractMemory class in namespace:QoS
257 MemCtrl(const QoSMemCtrlParams*);
259 virtual ~MemCtrl();
346 MemCtrl::escalateQueues(Queues& queues, uint64_t queue_entry_size,
418 MemCtrl::escalate(std::initializer_list<Queues*> queues,
466 MemCtrl::qosSchedule(std::initializer_list<Queues*> queues,
H A Dmem_sink.hh57 class MemSinkCtrl : public MemCtrl
H A Dmem_sink.cc48 : MemCtrl(p), requestLatency(p->request_latency),
67 MemCtrl::init();
113 return MemCtrl::getPort(interface, idx);
334 MemCtrl::regStats();
/gem5/src/mem/
H A Ddram_ctrl.cc63 QoS::MemCtrl(p),
191 MemCtrl::init();
488 logRequest(MemCtrl::READ, pkt->masterId(), pkt->qosValue(),
553 logRequest(MemCtrl::WRITE, pkt->masterId(), pkt->qosValue(),
1346 (busState==MemCtrl::READ)?"READ":"WRITE",
1492 logResponse(MemCtrl::READ, (*to_read)->masterId(),
1592 logResponse(MemCtrl::WRITE, dram_pkt->masterId(),
2505 MemCtrl::regStats();
2854 return QoS::MemCtrl::getPort(if_name, idx);
H A Ddram_ctrl.hh98 class DRAMCtrl : public QoS::MemCtrl

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