112968Sgiacomo.travaglini@arm.com/*
212968Sgiacomo.travaglini@arm.com * Copyright (c) 2018 ARM Limited
312968Sgiacomo.travaglini@arm.com * All rights reserved
412968Sgiacomo.travaglini@arm.com *
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612968Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual
712968Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating
812968Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software
912968Sgiacomo.travaglini@arm.com * licensed hereunder.  You may use the software subject to the license
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1512968Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are
1612968Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright
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3412968Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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3612968Sgiacomo.travaglini@arm.com *
3712968Sgiacomo.travaglini@arm.com * Authors: Matteo Andreozzi
3812968Sgiacomo.travaglini@arm.com */
3912968Sgiacomo.travaglini@arm.com
4012968Sgiacomo.travaglini@arm.com#include "turnaround_policy_ideal.hh"
4112968Sgiacomo.travaglini@arm.com
4212968Sgiacomo.travaglini@arm.com#include "params/QoSTurnaroundPolicyIdeal.hh"
4312968Sgiacomo.travaglini@arm.com
4412968Sgiacomo.travaglini@arm.comnamespace QoS {
4512968Sgiacomo.travaglini@arm.com
4612968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::TurnaroundPolicyIdeal(const Params* p)
4712968Sgiacomo.travaglini@arm.com  : TurnaroundPolicy(p)
4812968Sgiacomo.travaglini@arm.com{}
4912968Sgiacomo.travaglini@arm.com
5012968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::~TurnaroundPolicyIdeal()
5112968Sgiacomo.travaglini@arm.com{}
5212968Sgiacomo.travaglini@arm.com
5312968Sgiacomo.travaglini@arm.comMemCtrl::BusState
5412968Sgiacomo.travaglini@arm.comTurnaroundPolicyIdeal::selectBusState()
5512968Sgiacomo.travaglini@arm.com{
5612968Sgiacomo.travaglini@arm.com    auto bus_state = memCtrl->getBusState();
5712968Sgiacomo.travaglini@arm.com    const auto num_priorities = memCtrl->numPriorities();
5812968Sgiacomo.travaglini@arm.com
5912968Sgiacomo.travaglini@arm.com    // QoS-aware turnaround policy
6012968Sgiacomo.travaglini@arm.com    // Loop for every queue in the memory controller.
6112968Sgiacomo.travaglini@arm.com    for (uint8_t i = 0; i < num_priorities; i++) {
6212968Sgiacomo.travaglini@arm.com
6312968Sgiacomo.travaglini@arm.com        // Starting from top priority queues first
6412968Sgiacomo.travaglini@arm.com        uint8_t queue_idx = num_priorities - i - 1;
6512968Sgiacomo.travaglini@arm.com
6612968Sgiacomo.travaglini@arm.com        const uint64_t readq_size = memCtrl->getReadQueueSize(queue_idx);
6712968Sgiacomo.travaglini@arm.com        const uint64_t writeq_size = memCtrl->getWriteQueueSize(queue_idx);
6812968Sgiacomo.travaglini@arm.com
6912968Sgiacomo.travaglini@arm.com        // No data for current priority: both the read queue
7012968Sgiacomo.travaglini@arm.com        // and write queue are empty.
7112968Sgiacomo.travaglini@arm.com        if ((readq_size == 0) && (writeq_size == 0)) {
7212968Sgiacomo.travaglini@arm.com            continue;
7312968Sgiacomo.travaglini@arm.com        }
7412968Sgiacomo.travaglini@arm.com
7512968Sgiacomo.travaglini@arm.com        // Data found - select state
7612968Sgiacomo.travaglini@arm.com        if (readq_size == 0) {
7712968Sgiacomo.travaglini@arm.com            bus_state = MemCtrl::WRITE;
7812968Sgiacomo.travaglini@arm.com        } else if (writeq_size == 0) {
7912968Sgiacomo.travaglini@arm.com            bus_state = MemCtrl::READ;
8012968Sgiacomo.travaglini@arm.com        } else {
8112968Sgiacomo.travaglini@arm.com            // readq_size > 0 && writeq_size > 0
8212968Sgiacomo.travaglini@arm.com            bus_state = ((memCtrl->getBusState() == MemCtrl::READ) ?
8312968Sgiacomo.travaglini@arm.com                    MemCtrl::WRITE : MemCtrl::READ);
8412968Sgiacomo.travaglini@arm.com        }
8512968Sgiacomo.travaglini@arm.com
8612968Sgiacomo.travaglini@arm.com        DPRINTF(QOS,
8712968Sgiacomo.travaglini@arm.com                "QoSMemoryTurnaround::QoSTurnaroundPolicyIdeal - "
8812968Sgiacomo.travaglini@arm.com                "QoS priority %d queues %d, %d triggering bus %s "
8912968Sgiacomo.travaglini@arm.com                "in state %s\n", queue_idx, readq_size, writeq_size,
9012968Sgiacomo.travaglini@arm.com                (bus_state != memCtrl->getBusState()) ?
9112968Sgiacomo.travaglini@arm.com                "turnaround" : "staying",
9212968Sgiacomo.travaglini@arm.com                (bus_state == MemCtrl::READ)? "READ" : "WRITE");
9312968Sgiacomo.travaglini@arm.com        // State selected - exit loop
9412968Sgiacomo.travaglini@arm.com        break;
9512968Sgiacomo.travaglini@arm.com    }
9612968Sgiacomo.travaglini@arm.com
9712968Sgiacomo.travaglini@arm.com    return bus_state;
9812968Sgiacomo.travaglini@arm.com}
9912968Sgiacomo.travaglini@arm.com
10012968Sgiacomo.travaglini@arm.com} // namespace QoS
10112968Sgiacomo.travaglini@arm.com
10212968Sgiacomo.travaglini@arm.comQoS::TurnaroundPolicyIdeal *
10312968Sgiacomo.travaglini@arm.comQoSTurnaroundPolicyIdealParams::create()
10412968Sgiacomo.travaglini@arm.com{
10512968Sgiacomo.travaglini@arm.com    return new QoS::TurnaroundPolicyIdeal(this);
10612968Sgiacomo.travaglini@arm.com}
107