1/* 2 * Copyright (c) 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Matteo Andreozzi 38 */ 39 40#include "turnaround_policy_ideal.hh" 41 42#include "params/QoSTurnaroundPolicyIdeal.hh" 43 44namespace QoS { 45 46TurnaroundPolicyIdeal::TurnaroundPolicyIdeal(const Params* p) 47 : TurnaroundPolicy(p) 48{} 49 50TurnaroundPolicyIdeal::~TurnaroundPolicyIdeal() 51{} 52 53MemCtrl::BusState 54TurnaroundPolicyIdeal::selectBusState() 55{ 56 auto bus_state = memCtrl->getBusState(); 57 const auto num_priorities = memCtrl->numPriorities(); 58 59 // QoS-aware turnaround policy 60 // Loop for every queue in the memory controller. 61 for (uint8_t i = 0; i < num_priorities; i++) { 62 63 // Starting from top priority queues first 64 uint8_t queue_idx = num_priorities - i - 1; 65 66 const uint64_t readq_size = memCtrl->getReadQueueSize(queue_idx); 67 const uint64_t writeq_size = memCtrl->getWriteQueueSize(queue_idx); 68 69 // No data for current priority: both the read queue 70 // and write queue are empty. 71 if ((readq_size == 0) && (writeq_size == 0)) { 72 continue; 73 } 74 75 // Data found - select state 76 if (readq_size == 0) { 77 bus_state = MemCtrl::WRITE; 78 } else if (writeq_size == 0) { 79 bus_state = MemCtrl::READ; 80 } else { 81 // readq_size > 0 && writeq_size > 0 82 bus_state = ((memCtrl->getBusState() == MemCtrl::READ) ? 83 MemCtrl::WRITE : MemCtrl::READ); 84 } 85 86 DPRINTF(QOS, 87 "QoSMemoryTurnaround::QoSTurnaroundPolicyIdeal - " 88 "QoS priority %d queues %d, %d triggering bus %s " 89 "in state %s\n", queue_idx, readq_size, writeq_size, 90 (bus_state != memCtrl->getBusState()) ? 91 "turnaround" : "staying", 92 (bus_state == MemCtrl::READ)? "READ" : "WRITE"); 93 // State selected - exit loop 94 break; 95 } 96 97 return bus_state; 98} 99 100} // namespace QoS 101 102QoS::TurnaroundPolicyIdeal * 103QoSTurnaroundPolicyIdealParams::create() 104{ 105 return new QoS::TurnaroundPolicyIdeal(this); 106} 107