Searched refs:BaseCache (Results 1 - 18 of 18) sorted by relevance
| /gem5/src/mem/cache/prefetch/ |
| H A D | multi.hh | 54 void setCache(BaseCache *_cache) override;
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| H A D | base.hh | 64 class BaseCache;
261 BaseCache* cache;
339 virtual void setCache(BaseCache *_cache);
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| H A D | multi.cc | 52 MultiPrefetcher::setCache(BaseCache *_cache)
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| H A D | base.cc | 104 BasePrefetcher::setCache(BaseCache *_cache)
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| /gem5/src/mem/cache/ |
| H A D | queue_entry.hh | 55 class BaseCache;
160 virtual bool sendPacket(BaseCache &cache) = 0;
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| H A D | Cache.py | 75 class BaseCache(ClockedObject): class in inherits:ClockedObject
76 type = 'BaseCache'
147 class Cache(BaseCache):
152 class NoncoherentCache(BaseCache):
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| H A D | noncoherent_cache.cc | 68 : BaseCache(p, p->system->cacheLineSize())
79 BaseCache::satisfyRequest(pkt, blk);
86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
134 BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time);
146 BaseCache::recvTimingReq(pkt);
231 return BaseCache::recvAtomic(pkt);
241 BaseCache::functionalAccess(pkt, from_cpu_side);
334 BaseCache::recvTimingResp(pkt);
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| H A D | write_queue_entry.hh | 63 class BaseCache;
95 bool sendPacket(BaseCache &cache) override;
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| H A D | base.cc | 46 * Definition of BaseCache functions.
63 #include "params/BaseCache.hh"
69 BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
70 BaseCache *_cache,
79 BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) function in class:BaseCache
128 BaseCache::~BaseCache()
134 BaseCache::CacheSlavePort::setBlocked()
149 BaseCache
[all...] |
| H A D | base.hh | 49 * Declares a basic cache interface BaseCache.
93 class BaseCache : public ClockedObject class in inherits:ClockedObject
143 CacheMasterPort(const std::string &_name, BaseCache *_cache,
168 BaseCache &cache;
173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
222 BaseCache *cache;
236 MemSidePort(const std::string &_name, BaseCache *_cache,
263 CacheSlavePort(const std::string &_name, BaseCache *_cache,
290 BaseCache *cache;
307 CpuSidePort(const std::string &_name, BaseCache *_cach
[all...] |
| H A D | noncoherent_cache.hh | 71 class NoncoherentCache : public BaseCache
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| H A D | cache.hh | 69 class Cache : public BaseCache
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| H A D | write_queue_entry.cc | 142 WriteQueueEntry::sendPacket(BaseCache &cache)
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| H A D | cache.cc | 75 : BaseCache(p, p->system->cacheLineSize()),
84 BaseCache::satisfyRequest(pkt, blk);
180 BaseCache::evictBlock(old_blk, writebacks);
189 return BaseCache::access(pkt, blk, lat, writebacks);
323 BaseCache::handleTimingReqHit(pkt, blk, request_time);
402 BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time);
476 BaseCache::recvTimingReq(pkt);
677 return BaseCache::recvAtomic(pkt);
1417 return BaseCache::sendMSHRQueuePacket(mshr);
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| H A D | mshr.hh | 65 class BaseCache;
355 bool sendPacket(BaseCache &cache) override;
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| H A D | mshr.cc | 653 MSHR::sendPacket(BaseCache &cache)
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| /gem5/src/mem/cache/tags/ |
| H A D | compressed_tags.hh | 44 class BaseCache;
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| H A D | fa_lru.hh | 72 class BaseCache;
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