12810Srdreslin@umich.edu/* 212665Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2016,2018 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 4112665Snikos.nikoleris@arm.com * Nikos Nikoleris 422810Srdreslin@umich.edu */ 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu/** 452810Srdreslin@umich.edu * @file 462810Srdreslin@umich.edu * Declaration of a fully associative LRU tag store. 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 496216Snate@binkert.org#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 506216Snate@binkert.org#define __MEM_CACHE_TAGS_FA_LRU_HH__ 512810Srdreslin@umich.edu 5212727Snikos.nikoleris@arm.com#include <cstdint> 5312728Snikos.nikoleris@arm.com#include <functional> 5412727Snikos.nikoleris@arm.com#include <string> 5511168Sandreas.hansson@arm.com#include <unordered_map> 5613163Sodanrc@yahoo.com.br#include <vector> 572810Srdreslin@umich.edu 5812727Snikos.nikoleris@arm.com#include "base/bitfield.hh" 5912665Snikos.nikoleris@arm.com#include "base/intmath.hh" 6012727Snikos.nikoleris@arm.com#include "base/logging.hh" 6112727Snikos.nikoleris@arm.com#include "base/statistics.hh" 6212727Snikos.nikoleris@arm.com#include "base/types.hh" 6313223Sodanrc@yahoo.com.br#include "mem/cache/cache_blk.hh" 648229Snate@binkert.org#include "mem/cache/tags/base.hh" 6513752Sodanrc@yahoo.com.br#include "mem/packet.hh" 669796Sprakash.ramrakhyani@arm.com#include "params/FALRU.hh" 672810Srdreslin@umich.edu 6812665Snikos.nikoleris@arm.com// Uncomment to enable sanity checks for the FALRU cache and the 6912665Snikos.nikoleris@arm.com// TrackedCaches class 7012665Snikos.nikoleris@arm.com//#define FALRU_DEBUG 7112665Snikos.nikoleris@arm.com 7213216Sodanrc@yahoo.com.brclass BaseCache; 7312773Sodanrc@yahoo.com.brclass ReplaceableEntry; 7412773Sodanrc@yahoo.com.br 7512665Snikos.nikoleris@arm.com// A bitmask of the caches we are keeping track of. Currently the 7612665Snikos.nikoleris@arm.com// lowest bit is the smallest cache we are tracking, as it is 7712665Snikos.nikoleris@arm.com// specified by the corresponding parameter. The rest of the bits are 7812665Snikos.nikoleris@arm.com// for exponentially growing cache sizes. 7912665Snikos.nikoleris@arm.comtypedef uint32_t CachesMask; 8012665Snikos.nikoleris@arm.com 812810Srdreslin@umich.edu/** 822810Srdreslin@umich.edu * A fully associative cache block. 832810Srdreslin@umich.edu */ 842810Srdreslin@umich.educlass FALRUBlk : public CacheBlk 852810Srdreslin@umich.edu{ 8612636Sodanrc@yahoo.com.br public: 8713162Sodanrc@yahoo.com.br FALRUBlk() : CacheBlk(), prev(nullptr), next(nullptr), inCachesMask(0) {} 8813162Sodanrc@yahoo.com.br 892810Srdreslin@umich.edu /** The previous block in LRU order. */ 902810Srdreslin@umich.edu FALRUBlk *prev; 912810Srdreslin@umich.edu /** The next block in LRU order. */ 922810Srdreslin@umich.edu FALRUBlk *next; 932810Srdreslin@umich.edu 9412665Snikos.nikoleris@arm.com /** A bit mask of the caches that fit this block. */ 9512665Snikos.nikoleris@arm.com CachesMask inCachesMask; 9613222Sodanrc@yahoo.com.br 9713222Sodanrc@yahoo.com.br /** 9813222Sodanrc@yahoo.com.br * Pretty-print inCachesMask and other CacheBlk information. 9913222Sodanrc@yahoo.com.br * 10013222Sodanrc@yahoo.com.br * @return string with basic state information 10113222Sodanrc@yahoo.com.br */ 10213222Sodanrc@yahoo.com.br std::string print() const override; 1032810Srdreslin@umich.edu}; 1042810Srdreslin@umich.edu 1052810Srdreslin@umich.edu/** 1062810Srdreslin@umich.edu * A fully associative LRU cache. Keeps statistics for accesses to a number of 1072810Srdreslin@umich.edu * cache sizes at once. 1082810Srdreslin@umich.edu */ 1092810Srdreslin@umich.educlass FALRU : public BaseTags 1102810Srdreslin@umich.edu{ 1112810Srdreslin@umich.edu public: 1122810Srdreslin@umich.edu /** Typedef the block type used in this class. */ 1132810Srdreslin@umich.edu typedef FALRUBlk BlkType; 1146227Snate@binkert.org 1152810Srdreslin@umich.edu protected: 1162810Srdreslin@umich.edu /** The cache blocks. */ 1172810Srdreslin@umich.edu FALRUBlk *blks; 1182810Srdreslin@umich.edu 1192810Srdreslin@umich.edu /** The MRU block. */ 1202810Srdreslin@umich.edu FALRUBlk *head; 1212810Srdreslin@umich.edu /** The LRU block. */ 1222810Srdreslin@umich.edu FALRUBlk *tail; 1232810Srdreslin@umich.edu 1242810Srdreslin@umich.edu /** Hash table type mapping addresses to cache block pointers. */ 12512775Snikos.nikoleris@arm.com struct PairHash 12612775Snikos.nikoleris@arm.com { 12712775Snikos.nikoleris@arm.com template <class T1, class T2> 12812775Snikos.nikoleris@arm.com std::size_t operator()(const std::pair<T1, T2> &p) const 12912775Snikos.nikoleris@arm.com { 13012775Snikos.nikoleris@arm.com return std::hash<T1>()(p.first) ^ std::hash<T2>()(p.second); 13112775Snikos.nikoleris@arm.com } 13212775Snikos.nikoleris@arm.com }; 13312775Snikos.nikoleris@arm.com typedef std::pair<Addr, bool> TagHashKey; 13412775Snikos.nikoleris@arm.com typedef std::unordered_map<TagHashKey, FALRUBlk *, PairHash> TagHash; 1352810Srdreslin@umich.edu 1362810Srdreslin@umich.edu /** The address hash table. */ 13712775Snikos.nikoleris@arm.com TagHash tagHash; 1382810Srdreslin@umich.edu 1392810Srdreslin@umich.edu /** 1402810Srdreslin@umich.edu * Move a cache block to the MRU position. 14112648Sodanrc@yahoo.com.br * 1422810Srdreslin@umich.edu * @param blk The block to promote. 1432810Srdreslin@umich.edu */ 1442810Srdreslin@umich.edu void moveToHead(FALRUBlk *blk); 1452810Srdreslin@umich.edu 1462810Srdreslin@umich.edu /** 14712648Sodanrc@yahoo.com.br * Move a cache block to the LRU position. 14812648Sodanrc@yahoo.com.br * 14912648Sodanrc@yahoo.com.br * @param blk The block to demote. 15012648Sodanrc@yahoo.com.br */ 15112648Sodanrc@yahoo.com.br void moveToTail(FALRUBlk *blk); 15212648Sodanrc@yahoo.com.br 15312636Sodanrc@yahoo.com.br public: 1549796Sprakash.ramrakhyani@arm.com typedef FALRUParams Params; 1559796Sprakash.ramrakhyani@arm.com 1562810Srdreslin@umich.edu /** 1572810Srdreslin@umich.edu * Construct and initialize this cache tagstore. 1582810Srdreslin@umich.edu */ 1599796Sprakash.ramrakhyani@arm.com FALRU(const Params *p); 1609086Sandreas.hansson@arm.com ~FALRU(); 1612810Srdreslin@umich.edu 1622810Srdreslin@umich.edu /** 16313419Sodanrc@yahoo.com.br * Initialize blocks as FALRUBlk instances. 16413216Sodanrc@yahoo.com.br */ 16513419Sodanrc@yahoo.com.br void tagsInit() override; 16613216Sodanrc@yahoo.com.br 16713216Sodanrc@yahoo.com.br /** 1682810Srdreslin@umich.edu * Register the stats for this object. 1692810Srdreslin@umich.edu */ 17011169Sandreas.hansson@arm.com void regStats() override; 1712810Srdreslin@umich.edu 1722810Srdreslin@umich.edu /** 1733862Sstever@eecs.umich.edu * Invalidate a cache block. 1743862Sstever@eecs.umich.edu * @param blk The block to invalidate. 1752810Srdreslin@umich.edu */ 17611169Sandreas.hansson@arm.com void invalidate(CacheBlk *blk) override; 1772810Srdreslin@umich.edu 1782810Srdreslin@umich.edu /** 17911483Snikos.nikoleris@arm.com * Access block and update replacement data. May not succeed, in which 18011484Snikos.nikoleris@arm.com * case nullptr pointer is returned. This has all the implications of a 18111484Snikos.nikoleris@arm.com * cache access and should only be used as such. 18213418Sodanrc@yahoo.com.br * Returns tag lookup latency and the inCachesMask flags as a side effect. 18313418Sodanrc@yahoo.com.br * 1842810Srdreslin@umich.edu * @param addr The address to look for. 18510028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 18613418Sodanrc@yahoo.com.br * @param lat The latency of the tag lookup. 18712665Snikos.nikoleris@arm.com * @param in_cache_mask Mask indicating the caches in which the blk fits. 1882810Srdreslin@umich.edu * @return Pointer to the cache block. 1892810Srdreslin@umich.edu */ 19010815Sdavid.guillen@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 19112665Snikos.nikoleris@arm.com CachesMask *in_cache_mask); 19210815Sdavid.guillen@arm.com 19310815Sdavid.guillen@arm.com /** 19410815Sdavid.guillen@arm.com * Just a wrapper of above function to conform with the base interface. 19510815Sdavid.guillen@arm.com */ 19611870Snikos.nikoleris@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 1972810Srdreslin@umich.edu 1982810Srdreslin@umich.edu /** 1992810Srdreslin@umich.edu * Find the block in the cache, do not update the replacement data. 2002810Srdreslin@umich.edu * @param addr The address to look for. 20110028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 2022810Srdreslin@umich.edu * @param asid The address space ID. 2032810Srdreslin@umich.edu * @return Pointer to the cache block. 2042810Srdreslin@umich.edu */ 20511169Sandreas.hansson@arm.com CacheBlk* findBlock(Addr addr, bool is_secure) const override; 2062810Srdreslin@umich.edu 2072810Srdreslin@umich.edu /** 20812743Sodanrc@yahoo.com.br * Find a block given set and way. 20912743Sodanrc@yahoo.com.br * 21012743Sodanrc@yahoo.com.br * @param set The set of the block. 21112743Sodanrc@yahoo.com.br * @param way The way of the block. 21212743Sodanrc@yahoo.com.br * @return The block. 21312743Sodanrc@yahoo.com.br */ 21412743Sodanrc@yahoo.com.br ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 21512743Sodanrc@yahoo.com.br 21612743Sodanrc@yahoo.com.br /** 21712744Sodanrc@yahoo.com.br * Find replacement victim based on address. The list of evicted blocks 21812744Sodanrc@yahoo.com.br * only contains the victim. 21912600Sodanrc@yahoo.com.br * 22012600Sodanrc@yahoo.com.br * @param addr Address to find a victim for. 22112746Sodanrc@yahoo.com.br * @param is_secure True if the target memory space is secure. 22213941Sodanrc@yahoo.com.br * @param size Size, in bits, of new block to allocate. 22312744Sodanrc@yahoo.com.br * @param evict_blks Cache blocks to be evicted. 22412600Sodanrc@yahoo.com.br * @return Cache block to be replaced. 2252810Srdreslin@umich.edu */ 22612746Sodanrc@yahoo.com.br CacheBlk* findVictim(Addr addr, const bool is_secure, 22713941Sodanrc@yahoo.com.br const std::size_t size, 22812746Sodanrc@yahoo.com.br std::vector<CacheBlk*>& evict_blks) const override; 2295717Shsul@eecs.umich.edu 23012636Sodanrc@yahoo.com.br /** 23112636Sodanrc@yahoo.com.br * Insert the new block into the cache and update replacement data. 23212636Sodanrc@yahoo.com.br * 23313752Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 23412636Sodanrc@yahoo.com.br * @param blk The block to update. 23512636Sodanrc@yahoo.com.br */ 23613752Sodanrc@yahoo.com.br void insertBlock(const PacketPtr pkt, CacheBlk *blk) override; 2372810Srdreslin@umich.edu 2382810Srdreslin@umich.edu /** 2392810Srdreslin@umich.edu * Generate the tag from the addres. For fully associative this is just the 2402810Srdreslin@umich.edu * block address. 2412810Srdreslin@umich.edu * @param addr The address to get the tag from. 2422810Srdreslin@umich.edu * @return The tag. 2432810Srdreslin@umich.edu */ 24411169Sandreas.hansson@arm.com Addr extractTag(Addr addr) const override 2452810Srdreslin@umich.edu { 2462810Srdreslin@umich.edu return blkAlign(addr); 2472810Srdreslin@umich.edu } 2482810Srdreslin@umich.edu 2492810Srdreslin@umich.edu /** 25012574Sodanrc@yahoo.com.br * Regenerate the block address from the tag. 25112574Sodanrc@yahoo.com.br * 25212574Sodanrc@yahoo.com.br * @param block The block. 2532810Srdreslin@umich.edu * @return the block address. 2542810Srdreslin@umich.edu */ 25512574Sodanrc@yahoo.com.br Addr regenerateBlkAddr(const CacheBlk* blk) const override 2562810Srdreslin@umich.edu { 25712574Sodanrc@yahoo.com.br return blk->tag; 2582810Srdreslin@umich.edu } 2597612SGene.Wu@arm.com 26012728Snikos.nikoleris@arm.com void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 26112728Snikos.nikoleris@arm.com for (int i = 0; i < numBlocks; i++) { 26212728Snikos.nikoleris@arm.com visitor(blks[i]); 26312728Snikos.nikoleris@arm.com } 26412728Snikos.nikoleris@arm.com } 2659663Suri.wiener@arm.com 26612728Snikos.nikoleris@arm.com bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 2679347SAndreas.Sandberg@arm.com for (int i = 0; i < numBlocks; i++) { 26812728Snikos.nikoleris@arm.com if (visitor(blks[i])) { 26912728Snikos.nikoleris@arm.com return true; 27012728Snikos.nikoleris@arm.com } 2719347SAndreas.Sandberg@arm.com } 27212728Snikos.nikoleris@arm.com return false; 2739347SAndreas.Sandberg@arm.com } 27412665Snikos.nikoleris@arm.com 27512665Snikos.nikoleris@arm.com private: 27612665Snikos.nikoleris@arm.com /** 27712665Snikos.nikoleris@arm.com * Mechanism that allows us to simultaneously collect miss 27812665Snikos.nikoleris@arm.com * statistics for multiple caches. Currently, we keep track of 27912665Snikos.nikoleris@arm.com * caches from a set minimum size of interest up to the actual 28012665Snikos.nikoleris@arm.com * cache size. 28112665Snikos.nikoleris@arm.com */ 28212665Snikos.nikoleris@arm.com class CacheTracking 28312665Snikos.nikoleris@arm.com { 28412665Snikos.nikoleris@arm.com public: 28512665Snikos.nikoleris@arm.com CacheTracking(unsigned min_size, unsigned max_size, 28612665Snikos.nikoleris@arm.com unsigned block_size) 28712665Snikos.nikoleris@arm.com : blkSize(block_size), 28812665Snikos.nikoleris@arm.com minTrackedSize(min_size), 28912665Snikos.nikoleris@arm.com numTrackedCaches(max_size > min_size ? 29012665Snikos.nikoleris@arm.com floorLog2(max_size) - floorLog2(min_size) : 0), 29112665Snikos.nikoleris@arm.com inAllCachesMask(mask(numTrackedCaches)), 29213163Sodanrc@yahoo.com.br boundaries(numTrackedCaches) 29312665Snikos.nikoleris@arm.com { 29412665Snikos.nikoleris@arm.com fatal_if(numTrackedCaches > sizeof(CachesMask) * 8, 29512665Snikos.nikoleris@arm.com "Not enough bits (%s) in type CachesMask type to keep " 29612665Snikos.nikoleris@arm.com "track of %d caches\n", sizeof(CachesMask), 29712665Snikos.nikoleris@arm.com numTrackedCaches); 29812665Snikos.nikoleris@arm.com } 29912665Snikos.nikoleris@arm.com 30012665Snikos.nikoleris@arm.com /** 30112665Snikos.nikoleris@arm.com * Initialiaze cache blocks and the tracking mechanism 30212665Snikos.nikoleris@arm.com * 30312665Snikos.nikoleris@arm.com * All blocks in the cache need to be initialized once. 30412665Snikos.nikoleris@arm.com * 30512665Snikos.nikoleris@arm.com * @param blk the MRU block 30612665Snikos.nikoleris@arm.com * @param blk the LRU block 30712665Snikos.nikoleris@arm.com */ 30812665Snikos.nikoleris@arm.com void init(FALRUBlk *head, FALRUBlk *tail); 30912665Snikos.nikoleris@arm.com 31012665Snikos.nikoleris@arm.com /** 31112665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the MRU. 31212665Snikos.nikoleris@arm.com * 31312665Snikos.nikoleris@arm.com * For all caches that didn't fit the block before moving it, 31412665Snikos.nikoleris@arm.com * we move their boundaries one block closer to the MRU. We 31512665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 31612665Snikos.nikoleris@arm.com * 31712665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 31812665Snikos.nikoleris@arm.com */ 31912665Snikos.nikoleris@arm.com void moveBlockToHead(FALRUBlk *blk); 32012665Snikos.nikoleris@arm.com 32112665Snikos.nikoleris@arm.com /** 32212665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the LRU. 32312665Snikos.nikoleris@arm.com * 32412665Snikos.nikoleris@arm.com * For all caches that fitted the block before moving it, we 32512665Snikos.nikoleris@arm.com * move their boundaries one block closer to the LRU. We 32612665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 32712665Snikos.nikoleris@arm.com * 32812665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 32912665Snikos.nikoleris@arm.com */ 33012665Snikos.nikoleris@arm.com void moveBlockToTail(FALRUBlk *blk); 33112665Snikos.nikoleris@arm.com 33212665Snikos.nikoleris@arm.com /** 33312665Snikos.nikoleris@arm.com * Notify of a block access. 33412665Snikos.nikoleris@arm.com * 33512665Snikos.nikoleris@arm.com * This should be called every time a block is accessed and it 33612665Snikos.nikoleris@arm.com * updates statistics. If the input block is nullptr then we 33712665Snikos.nikoleris@arm.com * treat the access as a miss. The block's InCacheMask 33812665Snikos.nikoleris@arm.com * determines the caches in which the block fits. 33912665Snikos.nikoleris@arm.com * 34012665Snikos.nikoleris@arm.com * @param blk the block to record the access for 34112665Snikos.nikoleris@arm.com */ 34212665Snikos.nikoleris@arm.com void recordAccess(FALRUBlk *blk); 34312665Snikos.nikoleris@arm.com 34412665Snikos.nikoleris@arm.com /** 34512665Snikos.nikoleris@arm.com * Check that the tracking mechanism is in consistent state. 34612665Snikos.nikoleris@arm.com * 34712665Snikos.nikoleris@arm.com * Iterate from the head (MRU) to the tail (LRU) of the list 34812665Snikos.nikoleris@arm.com * of blocks and assert the inCachesMask and the boundaries 34912665Snikos.nikoleris@arm.com * are in consistent state. 35012665Snikos.nikoleris@arm.com * 35112665Snikos.nikoleris@arm.com * @param head the MRU block of the actual cache 35212665Snikos.nikoleris@arm.com * @param head the LRU block of the actual cache 35312665Snikos.nikoleris@arm.com */ 35413164Sodanrc@yahoo.com.br void check(const FALRUBlk *head, const FALRUBlk *tail) const; 35512665Snikos.nikoleris@arm.com 35612665Snikos.nikoleris@arm.com /** 35712665Snikos.nikoleris@arm.com * Register the stats for this object. 35812665Snikos.nikoleris@arm.com */ 35912665Snikos.nikoleris@arm.com void regStats(std::string name); 36012665Snikos.nikoleris@arm.com 36112665Snikos.nikoleris@arm.com private: 36212665Snikos.nikoleris@arm.com /** The size of the cache block */ 36312665Snikos.nikoleris@arm.com const unsigned blkSize; 36412665Snikos.nikoleris@arm.com /** The smallest cache we are tracking */ 36512665Snikos.nikoleris@arm.com const unsigned minTrackedSize; 36612665Snikos.nikoleris@arm.com /** The number of different size caches being tracked. */ 36712665Snikos.nikoleris@arm.com const int numTrackedCaches; 36812665Snikos.nikoleris@arm.com /** A mask for all cache being tracked. */ 36912665Snikos.nikoleris@arm.com const CachesMask inAllCachesMask; 37012665Snikos.nikoleris@arm.com /** Array of pointers to blocks at the cache boundaries. */ 37113163Sodanrc@yahoo.com.br std::vector<FALRUBlk*> boundaries; 37212665Snikos.nikoleris@arm.com 37312665Snikos.nikoleris@arm.com protected: 37412665Snikos.nikoleris@arm.com /** 37512665Snikos.nikoleris@arm.com * @defgroup FALRUStats Fully Associative LRU specific statistics 37612665Snikos.nikoleris@arm.com * The FA lru stack lets us track multiple cache sizes at once. These 37712665Snikos.nikoleris@arm.com * statistics track the hits and misses for different cache sizes. 37812665Snikos.nikoleris@arm.com * @{ 37912665Snikos.nikoleris@arm.com */ 38012665Snikos.nikoleris@arm.com 38112665Snikos.nikoleris@arm.com /** Hits in each cache */ 38212665Snikos.nikoleris@arm.com Stats::Vector hits; 38312665Snikos.nikoleris@arm.com /** Misses in each cache */ 38412665Snikos.nikoleris@arm.com Stats::Vector misses; 38512665Snikos.nikoleris@arm.com /** Total number of accesses */ 38612665Snikos.nikoleris@arm.com Stats::Scalar accesses; 38712665Snikos.nikoleris@arm.com 38812665Snikos.nikoleris@arm.com /** 38912665Snikos.nikoleris@arm.com * @} 39012665Snikos.nikoleris@arm.com */ 39112665Snikos.nikoleris@arm.com }; 39212665Snikos.nikoleris@arm.com CacheTracking cacheTracking; 3932810Srdreslin@umich.edu}; 3942810Srdreslin@umich.edu 3956216Snate@binkert.org#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 396