Searched refs:memory (Results 26 - 50 of 107) sorted by relevance
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/gem5/src/mem/cache/replacement_policies/ |
H A D | random_rp.cc | 34 #include <memory>
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H A D | fifo_rp.cc | 34 #include <memory>
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H A D | lfu_rp.cc | 34 #include <memory>
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H A D | lru_rp.cc | 34 #include <memory>
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H A D | mru_rp.cc | 34 #include <memory>
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H A D | brrip_rp.cc | 34 #include <memory>
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/gem5/src/sim/ |
H A D | syscall_desc.cc | 36 #include <memory>
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H A D | fd_array.hh | 40 #include <memory>
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H A D | arguments.hh | 35 #include <memory>
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/gem5/src/mem/ruby/system/ |
H A D | DMASequencer.hh | 32 #include <memory>
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/gem5/src/mem/ |
H A D | dramsim2.cc | 229 // a transaction matches the burst size of the memory (which we 257 // do the actual memory access which also turns the packet into a 311 // perform the actual memory access 359 : SlavePort(_name, &_memory), memory(_memory) function 366 ranges.push_back(memory.getAddrRange()); 373 return memory.recvAtomic(pkt); 379 memory.recvFunctional(pkt); 385 // pass it to the memory controller 386 return memory.recvTimingReq(pkt); 392 memory [all...] |
H A D | dramsim2.hh | 60 * The memory port has to deal with its own flow control to avoid 69 DRAMSim2& memory; member in class:DRAMSim2::MemoryPort
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H A D | simple_mem.hh | 59 * The simple memory is a basic single-ported memory controller with 88 SimpleMemory& memory; member in class:SimpleMemory::MemoryPort 118 * actual memory access. Note that this is where the packet spends 119 * the memory latency. 131 * Track the state of the memory as either idle or busy, no need 149 * Release the memory after being busy and send a retry if a
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H A D | backdoor.hh | 35 #include <memory>
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/gem5/ext/sst/tests/ |
H A D | test6_arm_4c.py | 99 "cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst" 169 memory = sst.Component("memory", "memHierarchy.MemController") variable 170 memory.addParams({ 204 sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))
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/gem5/src/systemc/ext/ |
H A D | systemc.h | 54 #include <memory>
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/gem5/src/mem/qos/ |
H A D | mem_sink.hh | 53 * The QoS Memory Sink is a lightweight memory controller with QoS 54 * support. It is meant to provide a QoS aware simple memory system 55 * without the need of using a complex DRAM memory controller 70 /** reference to parent memory object */ 71 MemSinkCtrl& memory; member in class:QoS::MemSinkCtrl::MemoryPort 89 * @param pkt pointer to memory packet 97 * @param pkt pointer to memory packet 104 * @param pkt pointer to memory packet 134 * Getter method to access this memory's slave port 138 * @return reference to this memory' [all...] |
/gem5/src/base/vnc/ |
H A D | vncinput.hh | 49 #include <memory>
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/gem5/src/systemc/utils/ |
H A D | report.hh | 35 #include <memory>
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/gem5/src/gpu-compute/ |
H A D | misc.hh | 41 #include <memory>
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | Message.hh | 33 #include <memory>
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/gem5/src/base/stats/ |
H A D | hdf5.hh | 45 #include <memory>
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/gem5/configs/ruby/ |
H A D | Ruby.py | 67 help="Should ruby maintain a second copy of memory") 105 # Sets bits to be used for interleaving. Creates memory controllers 107 # for each address range as the abstract memory can handle only one 114 dir_cntrl.memory = crossbar.slave 131 mem_ctrl.port = dir_cntrl.memory 223 # Create a backing copy of physical memory in case required 245 rom_dir_cntrl.memory = bootmem.port
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/gem5/src/systemc/dt/int/ |
H A D | sc_nbcommon.inc | 2355 // Allocate memory for the range. 2494 // Allocate memory for the range.
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/gem5/src/cpu/o3/ |
H A D | mem_dep_unit.hh | 47 #include <memory> 70 * Memory dependency unit class. This holds the memory dependence predictor. 71 * As memory operations are issued to the IQ, they are also issued to this 73 * upon. This unit must be checked prior to a memory operation being able 75 * memory dependence unit. This one is mostly for store sets; it will be 76 * quite limited in what other memory dependence predictions it can also 96 /** Frees up any memory allocated. */ 99 /** Returns the name of the memory dependence unit. */ 120 /** Inserts a memory instruction. */ 123 /** Inserts a non-speculative memory instructio [all...] |
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