Searched refs:memory (Results 26 - 50 of 107) sorted by relevance

12345

/gem5/src/mem/cache/replacement_policies/
H A Drandom_rp.cc34 #include <memory>
H A Dfifo_rp.cc34 #include <memory>
H A Dlfu_rp.cc34 #include <memory>
H A Dlru_rp.cc34 #include <memory>
H A Dmru_rp.cc34 #include <memory>
H A Dbrrip_rp.cc34 #include <memory>
/gem5/src/sim/
H A Dsyscall_desc.cc36 #include <memory>
H A Dfd_array.hh40 #include <memory>
H A Darguments.hh35 #include <memory>
/gem5/src/mem/ruby/system/
H A DDMASequencer.hh32 #include <memory>
/gem5/src/mem/
H A Ddramsim2.cc229 // a transaction matches the burst size of the memory (which we
257 // do the actual memory access which also turns the packet into a
311 // perform the actual memory access
359 : SlavePort(_name, &_memory), memory(_memory) function
366 ranges.push_back(memory.getAddrRange());
373 return memory.recvAtomic(pkt);
379 memory.recvFunctional(pkt);
385 // pass it to the memory controller
386 return memory.recvTimingReq(pkt);
392 memory
[all...]
H A Ddramsim2.hh60 * The memory port has to deal with its own flow control to avoid
69 DRAMSim2& memory; member in class:DRAMSim2::MemoryPort
H A Dsimple_mem.hh59 * The simple memory is a basic single-ported memory controller with
88 SimpleMemory& memory; member in class:SimpleMemory::MemoryPort
118 * actual memory access. Note that this is where the packet spends
119 * the memory latency.
131 * Track the state of the memory as either idle or busy, no need
149 * Release the memory after being busy and send a retry if a
H A Dbackdoor.hh35 #include <memory>
/gem5/ext/sst/tests/
H A Dtest6_arm_4c.py99 "cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst"
169 memory = sst.Component("memory", "memHierarchy.MemController") variable
170 memory.addParams({
204 sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))
/gem5/src/systemc/ext/
H A Dsystemc.h54 #include <memory>
/gem5/src/mem/qos/
H A Dmem_sink.hh53 * The QoS Memory Sink is a lightweight memory controller with QoS
54 * support. It is meant to provide a QoS aware simple memory system
55 * without the need of using a complex DRAM memory controller
70 /** reference to parent memory object */
71 MemSinkCtrl& memory; member in class:QoS::MemSinkCtrl::MemoryPort
89 * @param pkt pointer to memory packet
97 * @param pkt pointer to memory packet
104 * @param pkt pointer to memory packet
134 * Getter method to access this memory's slave port
138 * @return reference to this memory'
[all...]
/gem5/src/base/vnc/
H A Dvncinput.hh49 #include <memory>
/gem5/src/systemc/utils/
H A Dreport.hh35 #include <memory>
/gem5/src/gpu-compute/
H A Dmisc.hh41 #include <memory>
/gem5/src/mem/ruby/slicc_interface/
H A DMessage.hh33 #include <memory>
/gem5/src/base/stats/
H A Dhdf5.hh45 #include <memory>
/gem5/configs/ruby/
H A DRuby.py67 help="Should ruby maintain a second copy of memory")
105 # Sets bits to be used for interleaving. Creates memory controllers
107 # for each address range as the abstract memory can handle only one
114 dir_cntrl.memory = crossbar.slave
131 mem_ctrl.port = dir_cntrl.memory
223 # Create a backing copy of physical memory in case required
245 rom_dir_cntrl.memory = bootmem.port
/gem5/src/systemc/dt/int/
H A Dsc_nbcommon.inc2355 // Allocate memory for the range.
2494 // Allocate memory for the range.
/gem5/src/cpu/o3/
H A Dmem_dep_unit.hh47 #include <memory>
70 * Memory dependency unit class. This holds the memory dependence predictor.
71 * As memory operations are issued to the IQ, they are also issued to this
73 * upon. This unit must be checked prior to a memory operation being able
75 * memory dependence unit. This one is mostly for store sets; it will be
76 * quite limited in what other memory dependence predictions it can also
96 /** Frees up any memory allocated. */
99 /** Returns the name of the memory dependence unit. */
120 /** Inserts a memory instruction. */
123 /** Inserts a non-speculative memory instructio
[all...]

Completed in 29 milliseconds

12345