/gem5/src/arch/power/ |
H A D | decoder.hh | 50 Decoder(ISA* isa = nullptr) : instDone(false)
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/gem5/src/arch/mips/ |
H A D | decoder.hh | 52 Decoder(ISA* isa = nullptr) : instDone(false)
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/gem5/src/arch/riscv/ |
H A D | decoder.hh | 62 Decoder(ISA* isa=nullptr) { reset(); } argument
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/gem5/src/arch/arm/ |
H A D | decoder.hh | 99 Decoder(ISA* isa = nullptr);
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H A D | decoder.cc | 45 #include "arch/arm/isa.hh" 57 Decoder::Decoder(ISA* isa) argument 59 decoderFlavour(isa->decoderFlavour()) 64 sveLen = (isa->getCurSveVecLenInBitsAtReset() >> 7) - 1;
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H A D | pmu.cc | 45 #include "arch/arm/isa.hh" 497 assert(pmu.isa); 500 const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR)); 501 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
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/gem5/src/arch/sparc/ |
H A D | decoder.hh | 52 Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
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/gem5/src/sim/ |
H A D | root.cc | 131 std::string isa = THE_ISA_STR; local 132 SERIALIZE_SCALAR(isa);
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/gem5/configs/learning_gem5/part1/ |
H A D | simple.py | 90 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() variable 96 'tests/test-progs/hello/bin/', isa, 'linux/hello')
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H A D | two_level.py | 67 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() variable 73 'tests/test-progs/hello/bin/', isa, 'linux/hello')
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/gem5/src/cpu/ |
H A D | simple_thread.cc | 79 : ThreadState(_cpu, _thread_num, _process), isa(_isa), 90 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), 158 isa->startup(this);
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H A D | BaseCPU.py | 191 isa = ArchISAsParam([], "ISA instance") variable in class:BaseCPU 280 if len(self.isa) == 0: 281 self.isa = [ ArchISA() for i in range(self.numThreads) ] 283 if len(self.isa) != int(self.numThreads):
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/gem5/tests/gem5/ |
H A D | fixture.py | 155 "(--isa=), use --skip-build, or use 'rerun'.") 163 def __new__(cls, isa, variant, protocol=None): 164 target_dir = joinpath(config.build_dir, isa.upper()) 171 def _init(self, isa, variant, protocol=None): 180 self.options = [ '--default=' + isa.upper(), 229 def __init__(self, program, isa, os, recompile=False): 232 target = joinpath('bin', isa, os, program)
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/gem5/configs/learning_gem5/part3/ |
H A D | msi_caches.py | 112 isa = buildEnv['TARGET_ISA'] 113 if isa == 'x86': 117 if isa == 'x86' or isa == 'arm':
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H A D | ruby_caches_MI_example.py | 110 isa = buildEnv['TARGET_ISA'] 111 if isa == 'x86': 115 if isa == 'x86' or isa == 'arm':
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/gem5/tests/test-progs/asmtest/src/riscv/ |
H A D | Makefile | 2 # Makefile for riscv-tests/isa 7 src_dir := ./isa 44 $(RISCV_SIM) --isa=rv64gc $< 2> $@
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/gem5/tests/ |
H A D | run.py | 154 (category, mode, name, isa, opsys, config) = sys.argv[1].split('/')[-6:] 167 return joinpath(test_progs, app, 'bin', isa, opsys, file)
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H A D | tests.py | 117 parser.add_argument("--gpu-isa", type=str, default=None, 125 for isa, categories, modes in \ 128 for test in get_tests(isa, categories=categories, modes=modes, 144 test mode (fs or se), a workload name, an isa, an operating
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/gem5/ext/testlib/ |
H A D | config.py | 223 constants.isa_tag_type = 'isa' 264 constants.supported_isas = constants.supported_tags['isa'] 318 def default_isa(isa): 319 if not isa[0]: 322 return isa 358 config._add_post_processor('isa', default_isa) 461 '--isa', 581 common_args.isa.add_to(parser) 632 common_args.isa.add_to(parser) 653 common_args.isa [all...] |
/gem5/src/cpu/o3/ |
H A D | cpu.cc | 114 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])), 129 isa(numThreads, NULL), 223 isa[tid] = params->isa[tid]; 224 assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 622 isa[tid]->startup(threadContexts[tid]); 1171 return this->isa[tid]->readMiscRegNoEffect(misc_reg); 1179 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 1186 this->isa[ti [all...] |
H A D | thread_context_impl.hh | 203 cpu->isa[thread->threadId()]->clear(); 341 return cpu->isa[thread->threadId()]->flattenRegId(regId);
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/gem5/configs/common/ |
H A D | Simulation.py | 476 switch_cpus[i].isa = testsys.cpu[i].isa 517 repeat_switch_cpus[i].isa = testsys.cpu[i].isa 547 switch_cpus[i].isa = testsys.cpu[i].isa 548 switch_cpus_1[i].isa = testsys.cpu[i].isa
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/gem5/src/cpu/checker/ |
H A D | cpu.cc | 107 p->isa[0], false); 111 itb, dtb, p->isa[0]);
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/gem5/src/cpu/minor/ |
H A D | cpu.cc | 60 params->itb, params->dtb, params->isa[i]); 65 params->isa[i]);
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/gem5/util/ |
H A D | compile | 163 add_option('-i', "--all-isa", default=False, action='store_true', 245 for isa in isas: 248 build = valid[(isa, mode)]
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