19020Sgblack@eecs.umich.edu/* 210610SAndreas.Sandberg@ARM.com * Copyright (c) 2013-2014 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 149020Sgblack@eecs.umich.edu * Copyright (c) 2012 Google 159020Sgblack@eecs.umich.edu * All rights reserved. 169020Sgblack@eecs.umich.edu * 179020Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 189020Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 199020Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 209020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 219020Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 229020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 239020Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 249020Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 259020Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 269020Sgblack@eecs.umich.edu * this software without specific prior written permission. 279020Sgblack@eecs.umich.edu * 289020Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299020Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309020Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319020Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329020Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339020Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349020Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359020Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369020Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379020Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389020Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399020Sgblack@eecs.umich.edu * 409020Sgblack@eecs.umich.edu * Authors: Gabe Black 419020Sgblack@eecs.umich.edu */ 429020Sgblack@eecs.umich.edu 439020Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_DECODER_HH__ 449020Sgblack@eecs.umich.edu#define __ARCH_ARM_DECODER_HH__ 459020Sgblack@eecs.umich.edu 469023Sgblack@eecs.umich.edu#include <cassert> 479023Sgblack@eecs.umich.edu 489023Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 499023Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 509024Sgblack@eecs.umich.edu#include "arch/generic/decode_cache.hh" 519023Sgblack@eecs.umich.edu#include "base/types.hh" 529024Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 5311165SRekai.GonzalezAlberquilla@arm.com#include "enums/DecoderFlavour.hh" 549023Sgblack@eecs.umich.edu 559020Sgblack@eecs.umich.edunamespace ArmISA 569020Sgblack@eecs.umich.edu{ 579020Sgblack@eecs.umich.edu 5811165SRekai.GonzalezAlberquilla@arm.comclass ISA; 599022Sgblack@eecs.umich.educlass Decoder 609022Sgblack@eecs.umich.edu{ 619022Sgblack@eecs.umich.edu protected: 629023Sgblack@eecs.umich.edu //The extended machine instruction being generated 639023Sgblack@eecs.umich.edu ExtMachInst emi; 649023Sgblack@eecs.umich.edu MachInst data; 659023Sgblack@eecs.umich.edu bool bigThumb; 669023Sgblack@eecs.umich.edu bool instDone; 679023Sgblack@eecs.umich.edu bool outOfBytes; 689023Sgblack@eecs.umich.edu int offset; 699023Sgblack@eecs.umich.edu bool foundIt; 709023Sgblack@eecs.umich.edu ITSTATE itBits; 719023Sgblack@eecs.umich.edu 729374Sgblack@eecs.umich.edu int fpscrLen; 739374Sgblack@eecs.umich.edu int fpscrStride; 749374Sgblack@eecs.umich.edu 7513759Sgiacomo.gabrielli@arm.com /** 7613759Sgiacomo.gabrielli@arm.com * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN 7713759Sgiacomo.gabrielli@arm.com * bitfields. 7813759Sgiacomo.gabrielli@arm.com */ 7913759Sgiacomo.gabrielli@arm.com int sveLen; 8013759Sgiacomo.gabrielli@arm.com 8111165SRekai.GonzalezAlberquilla@arm.com Enums::DecoderFlavour decoderFlavour; 8211165SRekai.GonzalezAlberquilla@arm.com 8310610SAndreas.Sandberg@ARM.com /// A cache of decoded instruction objects. 8410610SAndreas.Sandberg@ARM.com static GenericISA::BasicDecodeCache defaultCache; 8510610SAndreas.Sandberg@ARM.com 8610610SAndreas.Sandberg@ARM.com /** 8710610SAndreas.Sandberg@ARM.com * Pre-decode an instruction from the current state of the 8810610SAndreas.Sandberg@ARM.com * decoder. 8910610SAndreas.Sandberg@ARM.com */ 9010610SAndreas.Sandberg@ARM.com void process(); 9110610SAndreas.Sandberg@ARM.com 9210610SAndreas.Sandberg@ARM.com /** 9310610SAndreas.Sandberg@ARM.com * Consume bytes by moving the offset into the data word and 9410610SAndreas.Sandberg@ARM.com * sanity check the results. 9510610SAndreas.Sandberg@ARM.com */ 9610610SAndreas.Sandberg@ARM.com void consumeBytes(int numBytes); 9710610SAndreas.Sandberg@ARM.com 9810610SAndreas.Sandberg@ARM.com public: // Decoder API 9911165SRekai.GonzalezAlberquilla@arm.com Decoder(ISA* isa = nullptr); 10010610SAndreas.Sandberg@ARM.com 10110610SAndreas.Sandberg@ARM.com /** Reset the decoders internal state. */ 10210610SAndreas.Sandberg@ARM.com void reset(); 10310610SAndreas.Sandberg@ARM.com 10410610SAndreas.Sandberg@ARM.com /** 10510610SAndreas.Sandberg@ARM.com * Can the decoder accept more data? 10610610SAndreas.Sandberg@ARM.com * 10710610SAndreas.Sandberg@ARM.com * A CPU model uses this method to determine if the decoder can 10810610SAndreas.Sandberg@ARM.com * accept more data. Note that an instruction can be ready (see 10910610SAndreas.Sandberg@ARM.com * instReady() even if this method returns true. 11010610SAndreas.Sandberg@ARM.com */ 11110610SAndreas.Sandberg@ARM.com bool needMoreBytes() const { return outOfBytes; } 11210610SAndreas.Sandberg@ARM.com 11310610SAndreas.Sandberg@ARM.com /** 11410610SAndreas.Sandberg@ARM.com * Is an instruction ready to be decoded? 11510610SAndreas.Sandberg@ARM.com * 11610610SAndreas.Sandberg@ARM.com * CPU models call this method to determine if decode() will 11710610SAndreas.Sandberg@ARM.com * return a new instruction on the next call. It typically only 11810610SAndreas.Sandberg@ARM.com * returns false if the decoder hasn't received enough data to 11910610SAndreas.Sandberg@ARM.com * decode a full instruction. 12010610SAndreas.Sandberg@ARM.com */ 12110610SAndreas.Sandberg@ARM.com bool instReady() const { return instDone; } 12210610SAndreas.Sandberg@ARM.com 12310610SAndreas.Sandberg@ARM.com /** 12410610SAndreas.Sandberg@ARM.com * Feed data to the decoder. 12510610SAndreas.Sandberg@ARM.com * 12610610SAndreas.Sandberg@ARM.com * A CPU model uses this interface to load instruction data into 12710610SAndreas.Sandberg@ARM.com * the decoder. Once enough data has been loaded (check with 12810610SAndreas.Sandberg@ARM.com * instReady()), a decoded instruction can be retrieved using 12910610SAndreas.Sandberg@ARM.com * decode(ArmISA::PCState). 13010610SAndreas.Sandberg@ARM.com * 13110610SAndreas.Sandberg@ARM.com * This method is intended to support both fixed-length and 13210610SAndreas.Sandberg@ARM.com * variable-length instructions. Instruction data is fetch in 13310610SAndreas.Sandberg@ARM.com * MachInst blocks (which correspond to the size of a typical 13410610SAndreas.Sandberg@ARM.com * insturction). The method might need to be called multiple times 13510610SAndreas.Sandberg@ARM.com * if the instruction spans multiple blocks, in that case 13610610SAndreas.Sandberg@ARM.com * needMoreBytes() will return true and instReady() will return 13710610SAndreas.Sandberg@ARM.com * false. 13810610SAndreas.Sandberg@ARM.com * 13910610SAndreas.Sandberg@ARM.com * The fetchPC parameter is used to indicate where in memory the 14010610SAndreas.Sandberg@ARM.com * instruction was fetched from. This is should be the same 14110610SAndreas.Sandberg@ARM.com * address as the pc. If fetching multiple blocks, it indicates 14210610SAndreas.Sandberg@ARM.com * where subsequent blocks are fetched from (pc + n * 14310610SAndreas.Sandberg@ARM.com * sizeof(MachInst)). 14410610SAndreas.Sandberg@ARM.com * 14510610SAndreas.Sandberg@ARM.com * @param pc Instruction pointer that we are decoding. 14610610SAndreas.Sandberg@ARM.com * @param fetchPC The address this chunk was fetched from. 14710610SAndreas.Sandberg@ARM.com * @param inst Raw instruction data. 14810610SAndreas.Sandberg@ARM.com */ 14910610SAndreas.Sandberg@ARM.com void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); 15010610SAndreas.Sandberg@ARM.com 15110610SAndreas.Sandberg@ARM.com /** 15210610SAndreas.Sandberg@ARM.com * Decode an instruction or fetch it from the code cache. 15310610SAndreas.Sandberg@ARM.com * 15410610SAndreas.Sandberg@ARM.com * This method decodes the currently pending pre-decoded 15510610SAndreas.Sandberg@ARM.com * instruction. Data must be fed to the decoder using moreBytes() 15610610SAndreas.Sandberg@ARM.com * until instReady() is true before calling this method. 15710610SAndreas.Sandberg@ARM.com * 15810610SAndreas.Sandberg@ARM.com * @param pc Instruction pointer that we are decoding. 15910610SAndreas.Sandberg@ARM.com * @return A pointer to a static instruction or NULL if the 16010610SAndreas.Sandberg@ARM.com * decoder isn't ready (see instReady()). 16110610SAndreas.Sandberg@ARM.com */ 16210610SAndreas.Sandberg@ARM.com StaticInstPtr decode(ArmISA::PCState &pc); 16310610SAndreas.Sandberg@ARM.com 16410610SAndreas.Sandberg@ARM.com /** 16510610SAndreas.Sandberg@ARM.com * Decode a pre-decoded machine instruction. 16610610SAndreas.Sandberg@ARM.com * 16710610SAndreas.Sandberg@ARM.com * @warn This method takes a pre-decoded instruction as its 16810610SAndreas.Sandberg@ARM.com * argument. It should typically not be called directly. 16910610SAndreas.Sandberg@ARM.com * 17010610SAndreas.Sandberg@ARM.com * @param mach_inst A pre-decoded instruction 17110610SAndreas.Sandberg@ARM.com * @retval A pointer to the corresponding StaticInst object. 17210610SAndreas.Sandberg@ARM.com */ 17310610SAndreas.Sandberg@ARM.com StaticInstPtr decode(ExtMachInst mach_inst, Addr addr) 1749023Sgblack@eecs.umich.edu { 17510610SAndreas.Sandberg@ARM.com return defaultCache.decode(this, mach_inst, addr); 1769023Sgblack@eecs.umich.edu } 1779023Sgblack@eecs.umich.edu 17810610SAndreas.Sandberg@ARM.com /** 17910610SAndreas.Sandberg@ARM.com * Decode a machine instruction without calling the cache. 18010610SAndreas.Sandberg@ARM.com * 18110610SAndreas.Sandberg@ARM.com * @note The implementation of this method is generated by the ISA 18210610SAndreas.Sandberg@ARM.com * parser script. 18310610SAndreas.Sandberg@ARM.com * 18410610SAndreas.Sandberg@ARM.com * @warn This method takes a pre-decoded instruction as its 18510610SAndreas.Sandberg@ARM.com * argument. It should typically not be called directly. 18610610SAndreas.Sandberg@ARM.com * 18710610SAndreas.Sandberg@ARM.com * @param mach_inst The binary instruction to decode. 18810610SAndreas.Sandberg@ARM.com * @retval A pointer to the corresponding StaticInst object. 18910610SAndreas.Sandberg@ARM.com */ 19010610SAndreas.Sandberg@ARM.com StaticInstPtr decodeInst(ExtMachInst mach_inst); 1919023Sgblack@eecs.umich.edu 19210610SAndreas.Sandberg@ARM.com /** 19310610SAndreas.Sandberg@ARM.com * Take over the state from an old decoder when switching CPUs. 19410610SAndreas.Sandberg@ARM.com * 19510610SAndreas.Sandberg@ARM.com * @param old Decoder used in old CPU 19610610SAndreas.Sandberg@ARM.com */ 19710610SAndreas.Sandberg@ARM.com void takeOverFrom(Decoder *old) {} 1989023Sgblack@eecs.umich.edu 1999023Sgblack@eecs.umich.edu 20010610SAndreas.Sandberg@ARM.com public: // ARM-specific decoder state manipulation 2019374Sgblack@eecs.umich.edu void setContext(FPSCR fpscr) 2029374Sgblack@eecs.umich.edu { 2039374Sgblack@eecs.umich.edu fpscrLen = fpscr.len; 2049374Sgblack@eecs.umich.edu fpscrStride = fpscr.stride; 2059374Sgblack@eecs.umich.edu } 20613759Sgiacomo.gabrielli@arm.com 20713759Sgiacomo.gabrielli@arm.com void setSveLen(uint8_t len) 20813759Sgiacomo.gabrielli@arm.com { 20913759Sgiacomo.gabrielli@arm.com sveLen = len; 21013759Sgiacomo.gabrielli@arm.com } 2119022Sgblack@eecs.umich.edu}; 2129020Sgblack@eecs.umich.edu 2139020Sgblack@eecs.umich.edu} // namespace ArmISA 2149020Sgblack@eecs.umich.edu 2159020Sgblack@eecs.umich.edu#endif // __ARCH_ARM_DECODER_HH__ 216