Searched refs:base (Results 101 - 125 of 167) sorted by relevance

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/gem5/src/arch/arm/insts/
H A Dmacromem.cc66 // Copy the base address register if we overwrite it, or if this instruction
349 IntRegIndex base, int64_t imm) :
358 *uop = new MicroLdFp16Uop(machInst, dest, base, imm);
360 *uop = new MicroStrQBFpXImmUop(machInst, dest, base, imm);
362 *++uop = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
370 IntRegIndex base, int64_t imm) :
379 *uop++ = new MicroLdFp16Uop(machInst, dest, base, 0);
381 *uop++= new MicroStrQBFpXImmUop(machInst, dest, base, 0);
382 *uop++ = new MicroStrQTFpXImmUop(machInst, dest, base, 0);
384 *uop = new MicroAddXiUop(machInst, base, bas
347 BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument
368 BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument
394 BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument
420 BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, IntRegIndex offset, ArmExtendType type, int64_t imm) argument
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/gem5/util/style/
H A Dverifiers.py126 def __init__(self, ui, opts, base=None):
128 self.base = base
143 if self.base is None:
146 abs_base = os.path.abspath(self.base)
/gem5/src/arch/x86/regs/
H A Dmisc.hh45 #include "base/bitunion.hh"
46 #include "base/logging.hh"
312 // Hidden segment base field
328 // The effective segment base, ie what is actually added to an
730 Bitfield<51, 12> physbase; // Range physical base address
824 Bitfield<51,12> physbase; // Range physical base address
881 setter(uint64_t &storage, uint32_t base) argument
883 replaceBits(storage, 63, 56, bits(base, 31, 24));
884 replaceBits(storage, 39, 16, bits(base, 23, 0));
918 BitfieldType<SegDescriptorBase> base; member in namespace:X86ISA
954 BitfieldType<SegDescriptorBase> base; member in namespace:X86ISA
984 Bitfield<31, 0> base; member in namespace:X86ISA
1052 Bitfield<51, 12> base; member in namespace:X86ISA
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/gem5/ext/pybind11/include/pybind11/
H A Dnumpy.h66 PyObject *base; member in struct:PyArray_Proxy
76 PyObject *base; member in struct:PyVoidScalarObject_Proxy
555 const void *ptr = nullptr, handle base = handle()) {
566 if (base && ptr) {
567 if (isinstance<array>(base))
568 /* Copy flags from base (except ownership bit) */
569 flags = reinterpret_borrow<array>(base).flags() & ~detail::npy_api::NPY_ARRAY_OWNDATA_;
582 if (base) {
583 api.PyArray_SetBaseObject_(tmp.ptr(), base.inc_ref().ptr());
591 array(const pybind11::dtype &dt, ShapeContainer shape, const void *ptr = nullptr, handle base
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H A Dcast.h108 // common base.
125 // `check` when adding just one base (which is typical--i.e. when there is no
141 * pybind-registered classes. Will be empty if neither the type nor any base classes are
315 * if the given type (or ValueType, if omitted) is not a pybind11 base of the given instance. If
337 "type is not a pybind11 base of the given instance "
341 std::string(find_type->type->tp_name) + "' is not a pybind11 base of the given `" +
352 pybind11_fail("instance allocation failed: new instance has no pybind11-registered base types");
363 else { // multiple base types or a too-large holder
679 for (auto base : bases) {
680 if (no_cpp_mi ? PyType_IsSubtype(base
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/gem5/ext/pybind11/tests/
H A Dtest_numpy_array.py163 def assert_references(a, b, base=None):
165 if base is None:
166 base = a
181 assert b.base is base
187 assert a1.flags.owndata and a1.base is None
192 assert a1.flags.owndata and a1.base is None
H A Dtest_class.cpp339 py::class_<NestBase> base(m, "NestBase");
340 base.def(py::init<>());
341 py::class_<Nested>(base, "Nested")
346 base.def("g", [](NestBase &, Nested &) {});
347 base.def("h", []() { return NestBase(); });
/gem5/ext/googletest/googlemock/scripts/
H A Dupload.py61 # Max size of patch or base file.
589 """Abstract base class providing an interface to the VCS."""
630 base_content: The contents of the base file.
663 """Uploads the base files (and if necessary, the current ones as well)."""
669 type = "base"
737 # SVN base URL is required to fetch files deleted in an older revision.
747 """Returns the SVN base URL.
761 logging.info("Removed username from base URL")
768 base = "http://svn.python.org/view/*checkout*%s/" % path
769 logging.info("Guessed Python base
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/gem5/ext/googletest/googletest/scripts/
H A Dupload.py61 # Max size of patch or base file.
589 """Abstract base class providing an interface to the VCS."""
630 base_content: The contents of the base file.
663 """Uploads the base files (and if necessary, the current ones as well)."""
669 type = "base"
737 # SVN base URL is required to fetch files deleted in an older revision.
747 """Returns the SVN base URL.
761 logging.info("Removed username from base URL")
768 base = "http://svn.python.org/view/*checkout*%s/" % path
769 logging.info("Guessed Python base
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/gem5/src/python/m5/
H A DSimObject.py89 # SimObjects inherit from a single SimObject base class). To specify
172 code('#include "base/str.hh"')
422 # and only allow "private" attributes to be passed to the base
492 base = bases[0]
495 # inherit all its settings from the base class. The only time
498 if isinstance(base, MetaSimObject):
499 cls._base = base
500 cls._params.parent = base._params
501 cls._ports.parent = base._ports
502 cls._values.parent = base
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/gem5/src/dev/arm/
H A Dgic_v3_its.cc148 const Addr base = its.pageAddress(Gicv3Its::DEVICE_TABLE); local
149 const Addr address = base + (device_id * sizeof(dte));
171 const Addr base = its.pageAddress(Gicv3Its::COLLECTION_TABLE); local
172 const Addr address = base + (collection_id * sizeof(cte));
183 const Addr base = its.pageAddress(Gicv3Its::DEVICE_TABLE); local
184 const Addr address = base + (device_id * sizeof(dte));
209 const Addr base = its.pageAddress(Gicv3Its::COLLECTION_TABLE); local
210 const Addr address = base + (collection_id * sizeof(cte));
1254 const BASER base = *base_it; local
1257 switch (base
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/gem5/src/arch/hsail/
H A Doperand.cc252 ((Brig::BrigOperandConstantBytes*)op_p)->base.byteCount
315 assert(op->base.kind == BRIG_KIND_OPERAND_ADDRESS);
449 assert(op->base.kind == BRIG_KIND_OPERAND_CODE_REF);
/gem5/src/gpu-compute/
H A Dhsail_code.cc67 if (code_dir->base.kind != BRIG_KIND_DIRECTIVE_FUNCTION &&
68 code_dir->base.kind != BRIG_KIND_DIRECTIVE_KERNEL) {
70 code_dir->base.kind);
87 // the instruction's byte address (relative to the base addr
/gem5/ext/mcpat/cacti/
H A Dbasic_circuit.h45 int powers (int base, int n);
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hh43 #include "base/trace.hh"
104 uint8_t scale, RegIndex index, RegIndex base,
/gem5/src/arch/x86/
H A Dtlb.cc52 #include "base/trace.hh"
243 AddrRange apicRange(localApicBase.base * PageBytes,
244 (localApicBase.base + 1) * PageBytes - 1);
311 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); local
317 Addr offset = bits(vaddr - base, size - 1, 0);
335 // The vaddr already has the segment base applied.
/gem5/src/arch/arm/
H A Dsemihosting.cc45 #include "base/logging.hh"
46 #include "base/time.hh"
599 "\tHeap base: 0x%x\n"
601 "\tStack base: 0x%x\n"
605 Addr base = argv[1]; local
609 proxy.write<uint64_t>(base + 0 * 8, heap_base, endian);
610 proxy.write<uint64_t>(base + 1 * 8, heap_limit, endian);
611 proxy.write<uint64_t>(base + 2 * 8, stack_base, endian);
612 proxy.write<uint64_t>(base + 3 * 8, stack_limit, endian);
614 proxy.write<uint32_t>(base
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/gem5/src/cpu/kvm/
H A Dx86_cpu.cc43 #include "cpu/kvm/base.hh"
191 seg.base, seg.limit, seg.selector, seg.type,
199 reg_name, dtable.base, dtable.limit);
384 // Check the register base
390 if (!isCanonicalAddress(seg.base))
391 warn("Illegal %s base: 0x%x\n", name, seg.base);
401 if (seg.base & 0xffffffff00000000ULL)
402 warn("Illegal %s base: 0x%x\n", name, seg.base);
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/gem5/src/base/
H A Dtime.hh45 #include "base/types.hh"
200 void serialize(const std::string &base, CheckpointOut &cp) const;
201 void unserialize(const std::string &base, CheckpointIn &cp);
/gem5/src/arch/mips/
H A Dfaults.hh90 virtual FaultVect base(ThreadContext *tc) const function in class:MipsISA::MipsFaultBase
102 return base(tc) + offset(tc);
/gem5/ext/sst/
H A Dgem5.cc60 #include <base/logging.hh>
61 #include <base/debug.hh>
/gem5/src/cpu/testers/memtest/
H A Dmemtest.cc47 #include "base/random.hh"
48 #include "base/statistics.hh"
49 #include "base/trace.hh"
227 unsigned base = random_mt.random(0, 1);
243 paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
/gem5/src/python/m5/util/
H A Dfdthelper.py56 # Make sure all values are ints (use automatic base detection if the
58 words = [long(w, base=0) if type(w) == str else long(w) for w in words]
76 # Make sure all values are ints (use automatic base detection if the
78 values = [int(v, base=0)
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbutils.h81 // This inline function returns the type of an i/o stream's base as a SystemC
82 // base designator.
83 // stream_object = reference to the i/o stream whose base is to be returned.
87 // This inline function returns true if the base should be shown when a SystemC
132 is_valid_base(sc_numrep base) argument
134 switch (base) {
144 "is_valid_base( sc_numrep base ) : "
149 std::sprintf( msg, "is_valid_base( sc_numrep base ) : "
150 "base = %s is not valid",
151 to_string( base )
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/gem5/ext/googletest/googlemock/test/
H A Dgmock-actions_test.cc572 Base base; local
574 Action<Base*()> ret = Return(&base);
575 EXPECT_EQ(&base, ret.Perform(make_tuple()));
658 Base base; local
660 Action<Base&()> a = ReturnRef(base);
661 EXPECT_EQ(&base, &a.Perform(make_tuple()));
682 Base base; local
684 Action<Base&()> a = ReturnRefOfCopy(base);
685 EXPECT_NE(&base, &a.Perform(make_tuple()));

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