1/*****************************************************************************
2 *                                McPAT/CACTI
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright 2012 Hewlett-Packard Development Company, L.P.
5 *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
6 *                          All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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31 ***************************************************************************/
32
33
34
35#ifndef __BASIC_CIRCUIT_H__
36#define __BASIC_CIRCUIT_H__
37
38#include "cacti_interface.h"
39#include "const.h"
40
41using namespace std;
42
43#define UNI_LEAK_STACK_FACTOR 0.43
44
45int powers (int base, int n);
46bool is_pow2(int64_t val);
47uint32_t _log2(uint64_t num);
48int factorial(int n, int m = 1);
49int combination(int n, int m);
50
51//#define DBG
52#ifdef DBG
53#define PRINTDW(a);\
54    a;
55#else
56#define PRINTDW(a);\
57
58#endif
59
60
61enum Wire_placement {
62    outside_mat,
63    inside_mat,
64    local_wires
65};
66
67
68
69enum Htree_type {
70    Add_htree,
71    Data_in_htree,
72    Data_out_htree,
73    Search_in_htree,
74    Search_out_htree,
75};
76
77enum Gate_type {
78    nmos,
79    pmos,
80    inv,
81    nand,
82    nor,
83    tri,
84    tg
85};
86
87enum Half_net_topology {
88    parallel,
89    series
90};
91
92double logtwo (double x);
93
94double gate_C(
95    double width,
96    double wirelength,
97    bool _is_dram = false,
98    bool _is_sram = false,
99    bool _is_wl_tr = false);
100
101double gate_C_pass(
102    double width,
103    double wirelength,
104    bool   _is_dram = false,
105    bool   _is_sram = false,
106    bool   _is_wl_tr = false);
107
108double drain_C_(
109    double width,
110    int nchannel,
111    int stack,
112    int next_arg_thresh_folding_width_or_height_cell,
113    double fold_dimension,
114    bool _is_dram = false,
115    bool _is_sram = false,
116    bool _is_wl_tr = false);
117
118double tr_R_on(
119    double width,
120    int nchannel,
121    int stack,
122    bool _is_dram = false,
123    bool _is_sram = false,
124    bool _is_wl_tr = false);
125
126double R_to_w(
127    double res,
128    int nchannel,
129    bool _is_dram = false,
130    bool _is_sram = false,
131    bool _is_wl_tr = false);
132
133double horowitz (
134    double inputramptime,
135    double tf,
136    double vs1,
137    double vs2,
138    int rise);
139
140double pmos_to_nmos_sz_ratio(
141    bool _is_dram = false,
142    bool _is_wl_tr = false);
143
144double simplified_nmos_leakage(
145    double nwidth,
146    bool _is_dram = false,
147    bool _is_cell = false,
148    bool _is_wl_tr = false);
149
150double simplified_pmos_leakage(
151    double pwidth,
152    bool _is_dram = false,
153    bool _is_cell = false,
154    bool _is_wl_tr = false);
155
156
157double cmos_Ileak(
158    double nWidth,
159    double pWidth,
160    bool _is_dram = false,
161    bool _is_cell = false,
162    bool _is_wl_tr = false);
163
164double cmos_Ig_n(
165    double nWidth,
166    bool _is_dram = false,
167    bool _is_cell = false,
168    bool _is_wl_tr = false);
169
170double cmos_Ig_p(
171    double pWidth,
172    bool _is_dram = false,
173    bool _is_cell = false,
174    bool _is_wl_tr = false);
175
176
177double cmos_Isub_leakage(
178    double nWidth,
179    double pWidth,
180    int    fanin,
181    enum Gate_type g_type,
182    bool _is_dram = false,
183    bool _is_cell = false,
184    bool _is_wl_tr = false,
185    enum Half_net_topology topo = series);
186
187double cmos_Ig_leakage(
188    double nWidth,
189    double pWidth,
190    int    fanin,
191    enum Gate_type g_type,
192    bool _is_dram = false,
193    bool _is_cell = false,
194    bool _is_wl_tr = false,
195    enum Half_net_topology topo = series);
196
197double shortcircuit(
198    double vt,
199    double velocity_index,
200    double c_in,
201    double c_out,
202    double w_nmos,
203    double w_pmos,
204    double i_on_n,
205    double i_on_p,
206    double i_on_n_in,
207    double i_on_p_in,
208    double vdd);
209
210double shortcircuit_simple(
211    double vt,
212    double velocity_index,
213    double c_in,
214    double c_out,
215    double w_nmos,
216    double w_pmos,
217    double i_on_n,
218    double i_on_p,
219    double i_on_n_in,
220    double i_on_p_in,
221    double vdd);
222//set power point product mask; strictly speaking this is not real point product
223inline void set_pppm(
224    double * pppv,
225    double a = 1,
226    double b = 1,
227    double c = 1,
228    double d = 1
229) {
230    pppv[0] = a;
231    pppv[1] = b;
232    pppv[2] = c;
233    pppv[3] = d;
234
235}
236
237inline void set_sppm(
238    double * sppv,
239    double a = 1,
240    double b = 1,
241    double c = 1,
242    double d = 1
243) {
244    sppv[0] = a;
245    sppv[1] = b;
246    sppv[2] = c;
247}
248
249#endif
250