Searched refs:Tick (Results 26 - 50 of 407) sorted by relevance
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/gem5/src/dev/ |
H A D | isa_fake.hh | 78 virtual Tick read(PacketPtr pkt); 85 virtual Tick write(PacketPtr pkt);
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H A D | baddev.cc | 50 Tick 57 Tick
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/gem5/src/dev/serial/ |
H A D | simple.hh | 54 Tick read(PacketPtr pkt) override; 55 Tick write(PacketPtr pkt) override;
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/gem5/src/sim/ |
H A D | debug.cc | 53 DebugBreakEvent(Tick when); 61 DebugBreakEvent::DebugBreakEvent(Tick when) 87 schedBreak(Tick when) 94 schedRelBreak(Tick delta) 111 takeCheckpoint(Tick when)
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H A D | pseudo_inst.hh | 48 //We need the "Tick" and "Addr" data types from here 81 void m5exit(ThreadContext *tc, Tick delay); 82 void m5fail(ThreadContext *tc, Tick delay, uint64_t code); 83 void resetstats(ThreadContext *tc, Tick delay, Tick period); 84 void dumpstats(ThreadContext *tc, Tick delay, Tick period); 85 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 86 void m5checkpoint(ThreadContext *tc, Tick dela [all...] |
H A D | core.cc | 49 Tick Frequency; 65 Tick s; 66 Tick ms; 67 Tick us; 68 Tick ns; 69 Tick ps; 78 // Default to 1 THz (1 Tick == 1 ps) 79 Tick _ticksPerSecond = 1e12; 115 setClockFrequency(Tick tps) 121 Tick getClockFrequenc [all...] |
/gem5/src/cpu/testers/traffic_gen/ |
H A D | trace_gen.hh | 83 Tick tick; 161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration, 182 Tick nextPacketTick(bool elastic, Tick delay) const; 198 mutable Tick tickOffset;
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H A D | dram_gen.hh | 91 MasterID master_id, Tick _duration, 94 Tick min_period, Tick max_period,
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.hh | 61 void reanalyzeMessages(Addr addr, Tick current_time); 62 void reanalyzeAllMessages(Tick current_time); 63 void stallMessage(Addr addr, Tick current_time); 66 bool isReady(Tick current_time) const; 69 delayHead(Tick current_time, Tick delta) 78 bool areNSlotsAvailable(unsigned int n, Tick curTime); 102 void enqueue(MsgPtr message, Tick curTime, Tick delta); 106 Tick dequeu [all...] |
/gem5/src/mem/ruby/slicc_interface/ |
H A D | Message.hh | 46 Message(Tick curTime) 80 void updateDelayedTicks(Tick curTime) 83 Tick delta = curTime - m_LastEnqueueTime; 86 Tick getDelayedTicks() const {return m_DelayedTicks;} 88 void setLastEnqueueTime(const Tick& time) { m_LastEnqueueTime = time; } 89 Tick getLastEnqueueTime() const {return m_LastEnqueueTime;} 91 Tick getTime() const { return m_time; } 107 const Tick m_time; 108 Tick m_LastEnqueueTime; // my last enqueue time 109 Tick m_DelayedTick [all...] |
/gem5/src/mem/ |
H A D | dram_ctrl.hh | 117 Tick recvAtomic(PacketPtr pkt); 153 Tick timeStamp; 156 Tick time_stamp) 181 Tick rdAllowedAt; 182 Tick wrAllowedAt; 183 Tick preAllowedAt; 184 Tick actAllowedAt; 304 Tick pwrStateTick; 309 Tick refreshDueAt; 369 * @param tick Tick whe [all...] |
H A D | mem_checker.hh | 89 static const Tick TICK_INITIAL = 0; 94 static const Tick TICK_FUTURE = MaxTick; 110 Tick _start, Tick _complete, 119 Tick start; //!< Start tick 120 Tick complete; //!< Completion tick 157 void startWrite(Serial serial, Tick _start, uint8_t data); 166 void completeWrite(Serial serial, Tick _complete); 181 Tick start; //!< Start of earliest write in cluster 182 Tick complet [all...] |
/gem5/src/mem/ruby/structures/ |
H A D | WireBuffer.hh | 75 void enqueue(MsgPtr message, Tick current_time, Tick delta); 76 void dequeue(Tick current_time); 78 void recycle(Tick current_time, Tick recycle_latency); 79 bool isReady(Tick current_time); 81 bool areNSlotsAvailable(int n, Tick current_time) { return true; };
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H A D | WireBuffer.cc | 73 WireBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) 76 Tick arrival_time = current_time + delta; 91 WireBuffer::dequeue(Tick current_time) 108 WireBuffer::recycle(Tick current_time, Tick recycle_latency) 118 Tick future_time = current_time + recycle_latency; 129 WireBuffer::isReady(Tick current_time)
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/gem5/src/dev/alpha/ |
H A D | tsunami_pchip.hh | 80 Tick read(PacketPtr pkt) override; 81 Tick write(PacketPtr pkt) override; 95 const Tick pioDelay;
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/gem5/src/dev/x86/ |
H A D | i8237.hh | 43 Tick latency; 58 Tick read(PacketPtr pkt) override; 60 Tick write(PacketPtr pkt) override;
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/gem5/src/mem/protocol/ |
H A D | atomic.cc | 51 Tick 58 Tick 68 Tick
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/gem5/src/mem/ruby/common/ |
H A D | Consumer.hh | 60 alreadyScheduled(Tick time) 66 insertScheduledWakeupTime(Tick time) 71 void scheduleEventAbsolute(Tick timeAbs); 77 std::set<Tick> m_scheduled_wakeups;
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/gem5/src/learning_gem5/part2/ |
H A D | hello_object.hh | 58 const Tick latency;
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/gem5/src/systemc/core/ |
H A D | sched_event.hh | 49 Tick _when; 56 schedule(ScEvents &events, Tick w) 83 void when(Tick w) { _when = w; } 84 Tick when() { return _when; }
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/gem5/src/cpu/simple/ |
H A D | noncaching.hh | 58 Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override;
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/gem5/src/mem/cache/ |
H A D | queue_entry.hh | 72 /** Tick when ready to issue */ 73 Tick readyTime; 88 const Tick recvTime; //!< Time when request was received (for stats) 89 const Tick readyTime; //!< Time when request is ready to be serviced 101 Target(PacketPtr _pkt, Tick ready_time, Counter _order)
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/gem5/src/arch/arm/kvm/ |
H A D | base_cpu.hh | 58 Tick kvmRun(Tick ticks) override;
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/gem5/src/dev/sparc/ |
H A D | dtod.hh | 63 Tick read(PacketPtr pkt) override; 64 Tick write(PacketPtr pkt) override;
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H A D | mm_disk.hh | 61 Tick read(PacketPtr pkt) override; 62 Tick write(PacketPtr pkt) override;
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Completed in 21 milliseconds
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