src/mem/dram_ctrl.hh

117         Tick recvAtomic(PacketPtr pkt);
153        Tick timeStamp;
156                          Tick time_stamp)
181         Tick rdAllowedAt;
182         Tick wrAllowedAt;
183         Tick preAllowedAt;
184         Tick actAllowedAt;
304         Tick pwrStateTick;
309         Tick refreshDueAt;
369          * @param tick Tick when transition should take place
371         void schedulePowerEvent(PowerState pwr_state, Tick tick);
415         Tick wakeUpAllowedAt;
443         std::deque<Tick> actTicks;
456          * @param ref_tick Tick for first refresh
458         void startup(Tick ref_tick);
540         void powerDownSleep(PowerState pwr_state, Tick tick);
549         void scheduleWakeUpEvent(Tick exit_delay);
639         const Tick entryTime;
642         Tick readyTime;
828     void accessAndRespond(PacketPtr pkt, Tick static_latency);
857         Tick extra_col_delay);
868             Tick extra_col_delay);
881     minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
894     void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
908                        Tick pre_at, bool trace = true);
987     const Tick M5_CLASS_VAR_USED tCK;
988     const Tick tRTW;
989     const Tick tCS;
990     const Tick tBURST;
991     const Tick tCCD_L_WR;
992     const Tick tCCD_L;
993     const Tick tRCD;
994     const Tick tCL;
995     const Tick tRP;
996     const Tick tRAS;
997     const Tick tWR;
998     const Tick tRTP;
999     const Tick tRFC;
1000     const Tick tREFI;
1001     const Tick tRRD;
1002     const Tick tRRD_L;
1003     const Tick tXAW;
1004     const Tick tXP;
1005     const Tick tXS;
1007     const Tick rankToRankDly;
1008     const Tick wrToRdDly;
1009     const Tick rdToWrDly;
1030     const Tick frontendLatency;
1037     const Tick backendLatency;
1042     Tick nextBurstAt;
1044     Tick prevArrival;
1052     Tick nextReqTime;
1141     Tick lastStatsResetTick;
1202     Tick recvAtomic(PacketPtr pkt);