1768SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3768SN/A * All rights reserved.
4768SN/A *
5768SN/A * Redistribution and use in source and binary forms, with or without
6768SN/A * modification, are permitted provided that the following conditions are
7768SN/A * met: redistributions of source code must retain the above copyright
8768SN/A * notice, this list of conditions and the following disclaimer;
9768SN/A * redistributions in binary form must reproduce the above copyright
10768SN/A * notice, this list of conditions and the following disclaimer in the
11768SN/A * documentation and/or other materials provided with the distribution;
12768SN/A * neither the name of the copyright holders nor the names of its
13768SN/A * contributors may be used to endorse or promote products derived from
14768SN/A * this software without specific prior written permission.
15768SN/A *
16768SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17768SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18768SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19768SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20768SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21768SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22768SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23768SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24768SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25768SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26768SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
29768SN/A */
30768SN/A
311722SN/A/** @file
321722SN/A * Tsunami PCI interface CSRs
33768SN/A */
34768SN/A
35768SN/A#ifndef __TSUNAMI_PCHIP_HH__
36768SN/A#define __TSUNAMI_PCHIP_HH__
37768SN/A
383540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh"
3911244Sandreas.sandberg@arm.com#include "dev/pci/host.hh"
404762Snate@binkert.org#include "params/TsunamiPChip.hh"
41768SN/A
421722SN/A/**
431722SN/A * A very simple implementation of the Tsunami PCI interface chips.
44768SN/A */
4511244Sandreas.sandberg@arm.comclass TsunamiPChip : public GenericPciHost
46768SN/A{
47768SN/A  protected:
482846SN/A
49896SN/A    /** Pchip control register */
50896SN/A    uint64_t pctl;
51896SN/A
52885SN/A    /** Window Base addresses */
53835SN/A    uint64_t wsba[4];
54885SN/A
55885SN/A    /** Window masks */
56835SN/A    uint64_t wsm[4];
57885SN/A
58885SN/A    /** Translated Base Addresses */
59835SN/A    uint64_t tba[4];
60768SN/A
61768SN/A  public:
624762Snate@binkert.org    typedef TsunamiPChipParams Params;
63885SN/A    /**
64885SN/A     * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
652539SN/A     * @param p pointer to the parameters struct
66885SN/A     */
674762Snate@binkert.org    TsunamiPChip(const Params *p);
684762Snate@binkert.org
694762Snate@binkert.org    const Params *
704762Snate@binkert.org    params() const
714762Snate@binkert.org    {
724762Snate@binkert.org        return dynamic_cast<const Params *>(_params);
734762Snate@binkert.org    }
74768SN/A
7511244Sandreas.sandberg@arm.com
7611244Sandreas.sandberg@arm.com    void serialize(CheckpointOut &cp) const override;
7711244Sandreas.sandberg@arm.com    void unserialize(CheckpointIn &cp) override;
7811244Sandreas.sandberg@arm.com
7911244Sandreas.sandberg@arm.com  public:
8011244Sandreas.sandberg@arm.com    Tick read(PacketPtr pkt) override;
8111244Sandreas.sandberg@arm.com    Tick write(PacketPtr pkt) override;
8211244Sandreas.sandberg@arm.com
8311244Sandreas.sandberg@arm.com    AddrRangeList getAddrRanges() const override;
8411244Sandreas.sandberg@arm.com
85885SN/A    /**
86885SN/A     * Translate a PCI bus address to a memory address for DMA.
87885SN/A     * @todo Andrew says this needs to be fixed. What's wrong with it?
8811244Sandreas.sandberg@arm.com     * @param pci_addr PCI address to translate.
89885SN/A     * @return memory system address
90885SN/A     */
9111244Sandreas.sandberg@arm.com    Addr dmaAddr(const PciBusAddr &addr, Addr pci_addr) const override;
92835SN/A
9311244Sandreas.sandberg@arm.com  protected:
9411244Sandreas.sandberg@arm.com    const AddrRange pioRange;
9511244Sandreas.sandberg@arm.com    const Tick pioDelay;
96768SN/A};
97768SN/A
98768SN/A#endif // __TSUNAMI_PCHIP_HH__
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