Searched refs:RegIndex (Results 26 - 40 of 40) sorted by relevance

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/gem5/src/cpu/o3/
H A Drename_map.hh103 void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);
216 RegIndex _intZeroReg,
217 RegIndex _floatZeroReg,
H A Drob.hh69 typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
H A Dcpu.cc229 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
230 RegIndex fpZeroReg =
244 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
252 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
264 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
272 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
283 for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) {
290 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
1358 FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1431 FullO3CPU<Impl>::setArchVecElem(const RegIndex
[all...]
H A Dcpu.hh453 const VecElem& readArchVecElem(const RegIndex& reg_idx,
477 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
H A Dregfile.hh179 PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.hh181 using MiscRegMap = std::unordered_map<std::string, RegIndex>;
/gem5/src/cpu/
H A Dbase_dyn_inst_impl.hh217 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
H A Dbase_dyn_inst.hh713 void markSrcRegReady(RegIndex src_idx);
/gem5/src/cpu/minor/
H A Ddyn_inst.cc146 RegIndex misc_reg = reg.index();
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc296 ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx,
342 ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
348 ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx,
355 ArmStaticInst::printVecPredReg(std::ostream &os, RegIndex reg_idx) const
361 ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
367 ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc252 const RegIndex reg_base(i * FP_REGS_PER_VFP_REG);
324 const RegIndex reg_base(i * FP_REGS_PER_VFP_REG);
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.cc104 RegIndex reg_idx = reg.index();
/gem5/src/arch/generic/
H A Dtypes.hh42 typedef uint16_t RegIndex; typedef
/gem5/src/arch/sparc/
H A Disa.cc97 RegIndex *mapChunk = intRegMap + offset;
107 RegIndex *mapChunk = intRegMap + offset;
H A Dua2005.cc72 getMiscRegName(RegIndex index)

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