Searched refs:Port (Results 101 - 125 of 158) sorted by relevance
1234567
| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 322 /** Port to connect to L1 instruction cache. */
325 /** Port to connect to L1 data cache. */
1149 Port &getInstPort() { return icachePort; }
1152 Port &getDataPort() { return dcachePort; }
|
| /gem5/src/python/m5/ |
| H A D | params.py | 1849 # Port objects
1855 # Port reference: encapsulates a reference to a particular port on a
1901 fatal("Port %s is already connected to %s, cannot connect %s\n",
1912 if not Port.is_compat(self, other):
1925 fatal("Port %s not connected, cannot splice in new peers\n", self)
1934 if Port.is_compat(old_peer, new_1) and Port.is_compat(self, new_2):
1939 elif Port.is_compat(old_peer, new_2) and Port.is_compat(self, new_1):
2074 # Port descriptio
2077 class Port(object): class in inherits:object
[all...] |
| /gem5/src/cpu/o3/ |
| H A D | cpu.hh | 738 Port &
745 Port &
|
| /gem5/src/dev/net/ |
| H A D | etherlink.cc | 91 Port &
|
| H A D | sinic.hh | 233 Port &getPort(const std::string &if_name,
|
| H A D | ns_gige.hh | 340 Port &getPort(const std::string &if_name,
|
| H A D | ethertap.cc | 162 Port &
|
| H A D | etherswitch.cc | 65 Port &
|
| /gem5/src/dev/ |
| H A D | dma_device.hh | 211 Port &getPort(const std::string &if_name,
|
| /gem5/src/gpu-compute/ |
| H A D | lds_state.hh | 150 * CuSidePort is the LDS Port closer to the CU side
439 Port &
|
| H A D | gpu_tlb.hh | 258 // CpuSidePort is the TLB Port closer to the CPU/CU side
280 * MemSidePort is the TLB Port closer to the memory side
311 Port &getPort(const std::string &if_name,
|
| /gem5/src/cpu/testers/memtest/ |
| H A D | memtest.cc | 125 Port &
|
| /gem5/src/cpu/testers/garnet_synthetic_traffic/ |
| H A D | GarnetSyntheticTraffic.cc | 112 Port &
|
| /gem5/src/cpu/testers/rubytest/ |
| H A D | RubyTester.cc | 131 Port &
|
| /gem5/src/mem/ |
| H A D | bridge.cc | 88 Port &
|
| H A D | dramsim2.cc | 339 Port &
|
| H A D | mem_checker_monitor.cc | 76 Port &
|
| H A D | serial_link.cc | 96 Port&
|
| /gem5/src/mem/qos/ |
| H A D | mem_sink.cc | 109 Port &
|
| /gem5/src/sim/ |
| H A D | system.hh | 130 * Additional function to return the Port of a memory object.
132 Port &getPort(const std::string &if_name,
142 * CPUs. SimObjects are expected to use Port::sendAtomic() and
143 * Port::recvAtomic() when accessing memory in this mode.
153 * SimObjects are expected to use Port::sendTiming() and
154 * Port::recvTiming() when accessing memory in this mode.
218 /** Port to physical memory used for writing object files into ram at
|
| H A D | cxx_manager.cc | 350 DPRINTF(CxxConfig, "Port not found: %s.%s,"
459 Port &master_port = master_object->getPort(
461 Port &slave_port = slave_object->getPort(
|
| /gem5/src/dev/arm/ |
| H A D | smmu_v3_slaveifc.cc | 92 Port&
|
| /gem5/src/dev/x86/ |
| H A D | i82094aa.cc | 77 Port &
|
| /gem5/src/dev/pci/ |
| H A D | copy_engine.cc | 116 Port &
132 Port &
|
| /gem5/src/cpu/checker/ |
| H A D | cpu.hh | 108 Port &
117 Port &
|
Completed in 45 milliseconds
1234567