Searched refs:Addr (Results 376 - 400 of 767) sorted by relevance

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/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.hh88 Addr paddr;
121 uint8_t _size, Addr _addr, uint64_t _data);
128 Addr paddr;
/gem5/src/mem/cache/prefetch/
H A Daccess_map_pattern_matching.hh141 Addr current, int stride) const
159 AccessMapEntry *getAccessMapEntry(Addr am_addr, bool is_secure);
168 void setEntryState(AccessMapEntry &entry, Addr block,
/gem5/src/mem/cache/tags/
H A Dbase_set_assoc.hh127 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
168 CacheBlk* findVictim(Addr addr, const bool is_secure,
229 Addr regenerateBlkAddr(const CacheBlk* blk) const override
H A Dcompressed_tags.hh110 CacheBlk* findVictim(Addr addr, const bool is_secure,
/gem5/src/arch/arm/linux/
H A Dprocess.hh80 static const Addr commPage;
/gem5/src/arch/arm/freebsd/
H A Dprocess.hh70 static const Addr commPage;
/gem5/src/arch/power/insts/
H A Dstatic_inst.cc59 PowerStaticInst::generateDisassembly(Addr pc,
H A Dinteger.hh95 Addr pc, const SymbolTable *symtab) const override;
118 Addr pc, const SymbolTable *symtab) const override;
139 Addr pc, const SymbolTable *symtab) const override;
175 Addr pc, const SymbolTable *symtab) const override;
/gem5/src/cpu/kvm/
H A Dvm.hh307 void setTSSAddress(Addr tss_address);
316 void coalesceMMIO(Addr start, int size);
388 void setupMemSlot(const MemSlot slot, void *host_addr, Addr guest_addr,
476 void *host_addr, Addr guest_addr,
/gem5/src/arch/sparc/insts/
H A Dnop.hh65 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
/gem5/src/arch/alpha/
H A Dremote_gdb.hh53 bool acc(Addr addr, size_t len) override;
/gem5/src/mem/cache/
H A Dmshr_queue.hh99 MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
H A Dcache_blk.cc46 CacheBlk::insert(const Addr tag, const bool is_secure,
/gem5/src/arch/arm/insts/
H A Dpseudo.cc62 const Addr pc(pc_state.instAddr());
103 DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
137 FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
178 WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
H A Dsve_mem.hh71 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
122 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
148 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
/gem5/src/arch/arm/
H A Dstage2_mmu.cc64 Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
101 Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
112 uint8_t *_data, Event *_event, Addr _oVAddr)
H A Dtable_walker.hh76 virtual Addr pfn() const = 0;
145 Addr paddr() const
152 Addr paddr(Addr va) const
161 Addr pfn() const
193 Addr l2Addr() const
332 Addr pfn() const
338 Addr paddr(Addr va) const
476 Addr pf
[all...]
/gem5/src/arch/riscv/
H A Dtypes.hh65 PCState(Addr val) : UPCState(val) { _compressed = false; _rv32 = false; }
H A Dremote_gdb.hh56 bool acc(Addr addr, size_t len);
/gem5/src/dev/arm/
H A DUFSHostDevice.py47 pio_addr = Param.Addr("Address for SCSI configuration slave interface")
H A DVirtIOMMIO.py52 pio_size = Param.Addr(4096, "IO range")
/gem5/src/dev/serial/
H A DUart.py58 pio_size = Param.Addr(0x4, "Size of address range")
/gem5/src/arch/x86/
H A Dmemhelpers.hh47 initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
107 readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
125 readPackedMemAtomic(ExecContext *xc, Addr addr, std::array<uint64_t, N> &mem,
141 readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
164 writePackedMem(ExecContext *xc, std::array<uint64_t, N> &mem, Addr addr,
177 unsigned dataSize, Addr addr, Request::Flags flags,
190 Addr addr, unsigned flags, uint64_t *res)
207 unsigned dataSize, Addr addr, Request::Flags flags,
224 Addr addr, unsigned flags, uint64_t *res)
H A Dtlb.cc97 TLB::insert(Addr vpn, const TlbEntry &entry)
121 TLB::lookup(Addr va, bool update_lru)
162 TLB::demapPage(Addr va, uint64_t asn)
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
191 req->setPaddr((Addr)regNum * sizeof(RegVal));
197 Addr IOPort = vaddr & ~IntAddrPrefixMask;
206 Addr configAddress =
230 Addr paddr = req->getPaddr();
285 Addr vadd
[all...]
/gem5/src/base/
H A Dremote_gdb.cc178 HardBreakpoint(BaseRemoteGDB *_gdb, PCEventQueue *q, Addr pc)
279 Addr
283 Addr r = 0;
318 std::map<Addr, HardBreakpoint *> hardBreakMap;
615 BaseRemoteGDB::read(Addr vaddr, size_t size, char *data)
617 static Addr lastaddr = 0;
646 BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data)
648 static Addr lastaddr = 0;
693 BaseRemoteGDB::insertSoftBreak(Addr addr, size_t len)
702 BaseRemoteGDB::removeSoftBreak(Addr add
[all...]

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