1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cstdint>
52#include <functional>
53#include <string>
54#include <vector>
55
56#include "base/logging.hh"
57#include "base/types.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/cache_blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/replacement_policies/replaceable_entry.hh"
62#include "mem/cache/tags/base.hh"
63#include "mem/cache/tags/indexing_policies/base.hh"
64#include "mem/packet.hh"
65#include "params/BaseSetAssoc.hh"
66
67/**
68 * A basic cache tag store.
69 * @sa  \ref gem5MemorySystem "gem5 Memory System"
70 *
71 * The BaseSetAssoc placement policy divides the cache into s sets of w
72 * cache lines (ways).
73 */
74class BaseSetAssoc : public BaseTags
75{
76  protected:
77    /** The allocatable associativity of the cache (alloc mask). */
78    unsigned allocAssoc;
79
80    /** The cache blocks. */
81    std::vector<CacheBlk> blks;
82
83    /** Whether tags and data are accessed sequentially. */
84    const bool sequentialAccess;
85
86    /** Replacement policy */
87    BaseReplacementPolicy *replacementPolicy;
88
89  public:
90    /** Convenience typedef. */
91     typedef BaseSetAssocParams Params;
92
93    /**
94     * Construct and initialize this tag store.
95     */
96    BaseSetAssoc(const Params *p);
97
98    /**
99     * Destructor
100     */
101    virtual ~BaseSetAssoc() {};
102
103    /**
104     * Initialize blocks as CacheBlk instances.
105     */
106    void tagsInit() override;
107
108    /**
109     * This function updates the tags when a block is invalidated. It also
110     * updates the replacement data.
111     *
112     * @param blk The block to invalidate.
113     */
114    void invalidate(CacheBlk *blk) override;
115
116    /**
117     * Access block and update replacement data. May not succeed, in which case
118     * nullptr is returned. This has all the implications of a cache access and
119     * should only be used as such. Returns the tag lookup latency as a side
120     * effect.
121     *
122     * @param addr The address to find.
123     * @param is_secure True if the target memory space is secure.
124     * @param lat The latency of the tag lookup.
125     * @return Pointer to the cache block if found.
126     */
127    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
128    {
129        CacheBlk *blk = findBlock(addr, is_secure);
130
131        // Access all tags in parallel, hence one in each way.  The data side
132        // either accesses all blocks in parallel, or one block sequentially on
133        // a hit.  Sequential access with a miss doesn't access data.
134        tagAccesses += allocAssoc;
135        if (sequentialAccess) {
136            if (blk != nullptr) {
137                dataAccesses += 1;
138            }
139        } else {
140            dataAccesses += allocAssoc;
141        }
142
143        // If a cache hit
144        if (blk != nullptr) {
145            // Update number of references to accessed block
146            blk->refCount++;
147
148            // Update replacement data of accessed block
149            replacementPolicy->touch(blk->replacementData);
150        }
151
152        // The tag lookup latency is the same for a hit or a miss
153        lat = lookupLatency;
154
155        return blk;
156    }
157
158    /**
159     * Find replacement victim based on address. The list of evicted blocks
160     * only contains the victim.
161     *
162     * @param addr Address to find a victim for.
163     * @param is_secure True if the target memory space is secure.
164     * @param size Size, in bits, of new block to allocate.
165     * @param evict_blks Cache blocks to be evicted.
166     * @return Cache block to be replaced.
167     */
168    CacheBlk* findVictim(Addr addr, const bool is_secure,
169                         const std::size_t size,
170                         std::vector<CacheBlk*>& evict_blks) const override
171    {
172        // Get possible entries to be victimized
173        const std::vector<ReplaceableEntry*> entries =
174            indexingPolicy->getPossibleEntries(addr);
175
176        // Choose replacement victim from replacement candidates
177        CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
178                                entries));
179
180        // There is only one eviction for this replacement
181        evict_blks.push_back(victim);
182
183        return victim;
184    }
185
186    /**
187     * Insert the new block into the cache and update replacement data.
188     *
189     * @param pkt Packet holding the address to update
190     * @param blk The block to update.
191     */
192    void insertBlock(const PacketPtr pkt, CacheBlk *blk) override
193    {
194        // Insert block
195        BaseTags::insertBlock(pkt, blk);
196
197        // Increment tag counter
198        tagsInUse++;
199
200        // Update replacement policy
201        replacementPolicy->reset(blk->replacementData);
202    }
203
204    /**
205     * Limit the allocation for the cache ways.
206     * @param ways The maximum number of ways available for replacement.
207     */
208    virtual void setWayAllocationMax(int ways) override
209    {
210        fatal_if(ways < 1, "Allocation limit must be greater than zero");
211        allocAssoc = ways;
212    }
213
214    /**
215     * Get the way allocation mask limit.
216     * @return The maximum number of ways available for replacement.
217     */
218    virtual int getWayAllocationMax() const override
219    {
220        return allocAssoc;
221    }
222
223    /**
224     * Regenerate the block address from the tag and indexing location.
225     *
226     * @param block The block.
227     * @return the block address.
228     */
229    Addr regenerateBlkAddr(const CacheBlk* blk) const override
230    {
231        return indexingPolicy->regenerateAddr(blk->tag, blk);
232    }
233
234    void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
235        for (CacheBlk& blk : blks) {
236            visitor(blk);
237        }
238    }
239
240    bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
241        for (CacheBlk& blk : blks) {
242            if (visitor(blk)) {
243                return true;
244            }
245        }
246        return false;
247    }
248};
249
250#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
251