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/gem5/src/arch/x86/isa/insts/general_purpose/flags/
H A Dpush_and_pop.py7872:b21a94bf6a28 Wed Feb 02 22:56:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Replace the stupd microop with a store/update sequence.
/gem5/ext/sst/
H A DExtMaster.hh10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A DExtSlave.hh10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A Dgem5.hh10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A Dlibgem5.cc10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
H A Dgem5.cc10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
/gem5/ext/sst/tests/
H A Dtest6_arm_4c.py10780:46070443051e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> config: Support full-system with SST's memory system

This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.
/gem5/src/kern/
H A Doperatingsystem.cc5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc
/gem5/src/doc/
H A Dpower_thermal_model.doxygen12678:b52646318166 Tue Apr 17 12:56:00 EDT 2018 Jason Lowe-Power <jason@lowepower.com> docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9981
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
/gem5/src/mem/cache/replacement_policies/
H A Dbip_rp.cc12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbip_rp.hh12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dlfu_rp.cc12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dlfu_rp.hh12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dfifo_rp.cc12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dfifo_rp.hh12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/sim/
H A Ddebug.hh9960:501c7384a5bc Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> sim: Clarify the difference between tracing and debugging

This patch changes the name the command-line options related to debug
output to all start with "debug" rather than being a mix of that and
"trace". It also makes it clear that the breakpoint time is specified
in ticks and not in cycles.
9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
H A DVoltageDomain.py10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dsemaphores.py6097:842991b33990 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of XADD.
6094:28198ab3adec Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of CMPXCHG.
/gem5/tests/configs/
H A Drealview-switcheroo-atomic.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
/gem5/src/base/
H A Dhostinfo.hh9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/
H A Dsimerr11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/
H A Dsimerr11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/
H A Dsimerr11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/
H A Dsimerr11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/generic/
H A Dmmapped_ipr.cc13344:0d881accc3ee Mon Oct 15 22:56:00 EDT 2018 Gabe Black <gabeblack@google.com> arch: Include some additional headers in arch/generic/mmapped_ipr.cc.

These had been included transitively before.

Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0
Reviewed-on: https://gem5-review.googlesource.com/c/13538
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

Completed in 32 milliseconds

1234567891011>>