History log of /gem5/ext/sst/libgem5.cc
Revision Date Author Comments
# 11618:37b0af2c7ba8 02-Sep-2016 Curtis Dunham <Curtis.Dunham@arm.com>

ext: eliminate warnings in SST connector

Now compiles completely clean.


# 11617:a51ae096ca25 24-Aug-2016 Curtis Dunham <Curtis.Dunham@arm.com>

commit 15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <Curtis.Dunham@arm.com>
ext: update SST connector for SST 6.0


# 10779:3e986011e99e 08-Apr-2015 Curtis Dunham <Curtis.Dunham@arm.com>

ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.