Searched hist:53 (Results 101 - 125 of 402) sorted by relevance
/gem5/src/mem/ | ||
H A D | secure_port_proxy.hh | 14196:ce364f5517f3 Thu Aug 15 19:53:00 EDT 2019 Gabe Black <gabeblack@google.com> mem: Make PortProxy use a delegate for a sendFunctional function. The only part of the MaserPort the PortProxy uses is the sendFunctional function which is part of the functional protocol. Rather than require a MasterPort which comes along with a lot of other mechanisms, this change slightly adjusts the PortProxy to only require that function through the use of a delegate. That allows lots of flexibility in how the actual packet gets sent and what sends it. In cases where code constructs a PortProxy and passes its constructor an unbound MasterPort, the PortProxy will create a delegate to the sendFunctional method on its own. This should also make it easier for objects which don't have traditional gem5 style ports, for instance systemc models, to implement just the little bit of the protocol they need, rather than having to stub out a whole port class, most of which will be ignored. Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | packet_access.hh | 12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/arm/linux/ | ||
H A D | linux.hh | 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power. 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/arm/ | ||
H A D | process.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
H A D | locked_mem.hh | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
H A D | vtophys.cc | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/x86/ | ||
H A D | decoder.hh | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
H A D | decoder.cc | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/mem/ruby/network/ | ||
H A D | Topology.cc | 9594:219ad5fe8c04 Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: convert Topology to regular class The Topology class in Ruby does not need to inherit from SimObject class. This patch turns it into a regular class. The topology object is now created in the constructor of the Network class. All the parameters for the topology class have been moved to the network class. 9593:9441ca79f3c8 Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move routers from topology to network |
/gem5/src/systemc/core/ | ||
H A D | sc_time.cc | 13263:bcd6d8140486 Thu Sep 27 01:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement the sc_time_tuple class. This class is non-standard and is an implementation detail in Accellera's implementation, but is referred to directly by the tests. It does the same thing as the time printing function, so rather than having duplicate code the printing function now uses the sc_time_tuple class even though it was doing fine on its own already. Change-Id: I69594ed0651f212ded6d979d60523bb3b0a789b1 Reviewed-on: https://gem5-review.googlesource.com/c/13189 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> 12983:fb1f462ae89e Thu Jul 19 19:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement some of the basics of sc_time. This is a very incomplete implementation, but is enough to unblock implementing some other dependent features. Change-Id: Ibd2f3476fe01389e277c6956d48337f551d14acd Reviewed-on: https://gem5-review.googlesource.com/12034 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | sc_prim.cc | 13189:057566bc8fd6 Fri Sep 07 19:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement the deprecated "timed_out" function. This function requires some slightly annoying bookkeeping since it doesn't just report whether the current process is running as a result of a timeout, it reports whether it's running as a result of a timeout *and* it could have been running from some other sensitivity instead. Pure timeouts don't count as timeouts which makes it harder to handle in a general way. Change-Id: I533d97fe66d20d7b83aba80f2ef45a8944668070 Reviewed-on: https://gem5-review.googlesource.com/c/12608 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/kern/linux/ | ||
H A D | linux.hh | 6684:04cba5a03e2e Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Implementation of the time system call. 6683:5e0fcc528fe5 Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Implementation of the times system call |
/gem5/src/mem/slicc/ast/ | ||
H A D | ObjDeclAST.py | 9595:470016acf37d Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: connect two controllers using only message buffers This patch modifies ruby so that two controllers can be connected to each other with only message buffers in between. Before this patch, all the controllers had to be connected to the network for them to communicate with each other. With this patch, one can have protocols where a controller is not connected to the network, but communicates with another controller through a message buffer. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | pred.isa | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/mips/linux/ | ||
H A D | linux.hh | 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power. |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ | ||
H A D | config.ini | 9183:8ee71266699b Wed Sep 05 21:53:00 EDT 2012 Joel Hestness <hestness@cs.wisc.edu> stats: Update Ruby regressions for memory controller fix |
/gem5/src/cpu/kvm/ | ||
H A D | vm.cc | 10605:8fc6e7a835d1 Wed Dec 10 00:53:00 EST 2014 Gabe Black <gabeblack@google.com> Let other objects set up memory like regions in a KVM VM. |
/gem5/src/mem/ruby/common/ | ||
H A D | Consumer.hh | 9600:34df8f24be7e Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: consumer: avoid using receiver side clock A set of patches was recently committed to allow multiple clock domains in ruby. In those patches, I had inadvertently made an incorrect use of the clocks. Suppose object A needs to schedule an event on object B. It was possible that A accesses B's clock to schedule the event. This is not possible in actual system. Hence, changes are being to the Consumer class so as to avoid such happenings. Note that in a multi eventq simulation, this can possibly lead to an incorrect simulation. There are two functions in the Consumer class that are used for scheduling events. The first function takes in the relative delay over the current time as the argument and adds the current time to it for scheduling the event. The second function takes in the absolute time (in ticks) for scheduling the event. The first function is now being moved to protected section of the class so that only objects of the derived classes can use it. All other objects will have to specify absolute time while scheduling an event for some consumer. |
/gem5/src/unittest/ | ||
H A D | stattest.cc | 7504:ad631c296c9b Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> stats: cleanup a few small problems in stats |
/gem5/src/arch/power/ | ||
H A D | isa_traits.hh | 6974:4d4903a3e7c5 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> O3PCU: Split loads and stores that cross cache line boundaries. When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. |
/gem5/src/arch/arm/isa/ | ||
H A D | bitfields.isa | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/riscv/ | ||
H A D | tlb.cc | 11962:43ce94c4d34c Tue Mar 21 00:53:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: fix error on memory op address overflow Previously, if a memory operation referenced an address that caused the data to wrap around to the beginning of the memory (such as -1 or 0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and gem5 would crash. This patch fixes that by checking for such a case in RISC-V's TLB code and returning a fault from translateData if that would happen. Because RISC-V does support unaligned memory accesses, no checking is performed to make sure that an access doesn't cross a cache line. [Update creation of page table fault to use make_shared.] [Add comment explaining the change and assertion that the memory request isn't zero size.] Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410 Reviewed-on: https://gem5-review.googlesource.com/2345 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/cpu/ | ||
H A D | translation.hh | 6973:a123bd350935 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> BaseDynInst: Make the TLB translation timing instead of atomic. This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class. |
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | SConscript | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/configs/common/ | ||
H A D | SysPaths.py | 12233:53cf2e32cb59 Mon Oct 30 21:31:00 EDT 2017 Gabe Black <gabeblack@google.com> config: Rework the SysPaths functions into functors. These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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